hw/intc/arm_gicv5: Create backing state for SPIs
The GICv5 allows an IRS to implement SPIs, which are fixed-wire interrupts connected directly to the IRS. For QEMU we want to use these for all our traditional fixed-wire interrupt devices. (The other option the architecture permits is an Interrupt Wire Bridge (IWB), which converts from a fixed-wire interrupt to an interrupt event that is then translated through an ITS to send an LPI to the ITS -- this is much more complexity than we need or want.) SPI configuration is set via the same CPUIF instructions as LPI configuration. Create an array of structs which track the SPI state information listed in I_JVVTZ and I_BWPPP (ignoring for the moment the VM assignment state, which we will add when we add virtualization support). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-24-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
df055f4c3935db9b55f224e6ccf5bb8e877a6d94
3 files changed
+71
hw/intc/arm_gicv5_common.c
+30
@@ -64,6 +64,34 @@ static void gicv5_common_reset_hold(Object *obj, ResetType type)
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memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser));
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memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr));
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+
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+ if (cs->spi) {
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+ GICv5Domain mp_domain;
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+
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+ /*
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+ * D_YGLYC, D_TVVRZ: SPIs reset to edge-triggered, inactive,
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+ * idle, disabled, targeted routing mode, not assigned to a
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+ * VM, and assigned to the most-privileged interrupt domain.
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+ * Other state is UNKNOWN: we choose to zero it.
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+ */
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+ memset(cs->spi, 0, cs->spi_irs_range * sizeof(*cs->spi));
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+
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+ /*
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+ * The most-privileged interrupt domain is effectively the
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+ * first in the list (EL3, S, NS) that we implement.
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+ */
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+ if (gicv5_domain_implemented(cs, GICV5_ID_EL3)) {
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+ mp_domain = GICV5_ID_EL3;
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+ } else if (gicv5_domain_implemented(cs, GICV5_ID_S)) {
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+ mp_domain = GICV5_ID_S;
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+ } else {
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+ mp_domain = GICV5_ID_NS;
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+ }
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+
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+ for (int i = 0; i < cs->spi_irs_range; i++) {
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+ cs->spi[i].domain = mp_domain;
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+ }
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+ }
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}
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static void gicv5_common_init(Object *obj)
@@ -142,6 +170,8 @@ static void gicv5_common_realize(DeviceState *dev, Error **errp)
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address_space_init(&cs->dma_as, cs->dma, "gicv5-sysmem");
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+ cs->spi = g_new0(GICv5SPIState, cs->spi_irs_range);
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+
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trace_gicv5_common_realize(cs->irsid, cs->num_cpus,
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cs->spi_base, cs->spi_irs_range, cs->spi_range);
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}
include/hw/intc/arm_gicv5_common.h
+27
@@ -55,6 +55,25 @@
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OBJECT_DECLARE_TYPE(GICv5Common, GICv5CommonClass, ARM_GICV5_COMMON)
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+/*
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+ * This is where we store the state the IRS handles for an SPI.
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+ * Generally this corresponds to the spec's list of state in I_JVVTZ
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+ * and J_BWPPP. level is a QEMU implementation detail and is where we
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+ * store the actual current state of the incoming qemu_irq line.
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+ */
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+typedef struct GICv5SPIState {
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+ uint32_t iaffid;
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+ uint8_t priority;
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+ bool level;
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+ bool pending;
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+ bool active;
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+ bool enabled;
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+ GICv5HandlingMode hm;
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+ GICv5RoutingMode irm;
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+ GICv5TriggerMode tm;
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+ GICv5Domain domain;
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+} GICv5SPIState;
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+
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/*
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* This class is for common state that will eventually be shared
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* between TCG and KVM implementations of the GICv5.
@@ -67,6 +86,14 @@ struct GICv5Common {
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uint64_t irs_ist_baser[NUM_GICV5_DOMAINS];
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uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS];
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+ /*
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+ * Pointer to an array of state information for the SPIs. Array
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+ * element 0 is SPI ID s->spi_base, and there are s->spi_irs_range
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+ * elements in total. SPI state is not per-domain: SPI is
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+ * configurable to a particular domain via IRS_SPI_DOMAINR.
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+ */
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+ GICv5SPIState *spi;
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+
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/* Bits here are set for each physical interrupt domain implemented */
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uint8_t implemented_domains;
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include/hw/intc/arm_gicv5_types.h
+14
@@ -70,4 +70,18 @@ typedef enum GICv5RoutingMode {
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GICV5_1OFN = 1,
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} GICv5RoutingMode;
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+/*
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+ * Interrupt trigger mode (same encoding as IRS_SPI_CFGR.TM) Note that
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+ * this is not the same thing as handling mode, even though the two
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+ * possible states have the same names. Trigger mode applies only for
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+ * SPIs and tells the IRS what kinds of changes to the input signal
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+ * wire should make it generate SET and CLEAR events. Handling mode
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+ * affects whether the pending state of an interrupt is cleared when
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+ * the interrupt is acknowledged, and applies to both SPIs and LPIs.
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+ */
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+typedef enum GICv5TriggerMode {
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+ GICV5_TRIGGER_EDGE = 0,
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+ GICV5_TRIGGER_LEVEL = 1,
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+} GICv5TriggerMode;
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+
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#endif