@samitouri / QOSamiQemu / commits / e07077a766

hw/char: Check interrupt after txctrl register is written

It's possible that the transmit watermark level (txctrl.txcnt) is updated when the user writes to txctrl register, which may decrease the transmit watermark level to less than the number of entries in the transmit FIFO. In such a case, the interrupt should be raised so we need to call sifive_uart_update_irq() to check and update interrupt when txctrl register is written. Otherwise, the interrupt will have to be delayed until next TX FIFO transmission is processed. Suggested-by: Chao Liu <chao.liu.zevorn@gmail.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260513030503.3665414-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Frank Chang committed May 13, 2026 at 11:05 UTC e07077a766071418e76d1c7db7e51e344776eaf2
1 file changed +1
hw/char/sifive_uart.c
+1
@@ -213,6 +213,7 @@ sifive_uart_write(void *opaque, hwaddr addr,
213 if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s->tx_fifo)) {
214 sifive_uart_trigger_tx_fifo(s);
215 }
216 + sifive_uart_update_irq(s);
217 return;
218 case SIFIVE_UART_RXCTRL:
219 s->rxctrl = val64;