target/riscv: Replace MO_TE by mo_endian (Zilsd extension)
Replace compile-time MO_TE evaluation by runtime mo_endian() one, which expand target endianness from DisasContext. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260318103122.97244-13-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Philippe Mathieu-Daudé committed
Mar 18, 2026 at 11:31 UTC
e3527cb4b92bc8d18b61db6213cb2d4f3b541f21
1 file changed
+2
-2
target/riscv/insn_trans/trans_zilsd.c.inc
+2
-2
@@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
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TCGv addr = get_address(ctx, a->rs1, a->imm);
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TCGv_i64 tmp = tcg_temp_new_i64();
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- tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
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+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
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if (a->rd == 0) {
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return true;
@@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
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} else {
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tcg_gen_concat_tl_i64(tmp, data_low, data_high);
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}
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- tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
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+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
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return true;
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}