hw/arm/fsl-imx8mm: Add PCIe support
This enables support for Designware PCI Express Controller emulation It provides a controlled environment to debug the linux pci subsystem Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gaurav Sharma committed
Apr 21, 2026 at 12:22 UTC
e7a2a4cd78107a1fc7c3e1b7491ce3e4d2ffcf18
3 files changed
+43
hw/arm/Kconfig
+3
@@ -619,11 +619,14 @@ config FSL_IMX8MP_EVK
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config FSL_IMX8MM
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bool
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+ imply PCI_DEVICES
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select ARM_GIC
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select FSL_IMX8MP_ANALOG
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select FSL_IMX8MP_CCM
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select IMX
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select SDHCI
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+ select PCI_EXPRESS_DESIGNWARE
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+ select PCI_EXPRESS_FSL_IMX8M_PHY
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config FSL_IMX8MM_EVK
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bool
hw/arm/fsl-imx8mm.c
+30
@@ -184,6 +184,10 @@ static void fsl_imx8mm_init(Object *obj)
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g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
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object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
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}
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+
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+ object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
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+ object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
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+ TYPE_FSL_IMX8M_PCIE_PHY);
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}
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static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
@@ -388,6 +392,30 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,
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fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr);
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+ /* PCIe */
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+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {
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+ return;
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+ }
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+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0,
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+ fsl_imx8mm_memmap[FSL_IMX8MM_PCIE1].addr);
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+
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0,
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+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTA_IRQ));
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1,
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+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTB_IRQ));
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2,
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+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTC_IRQ));
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3,
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+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTD_IRQ));
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4,
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+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_MSI_IRQ));
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+
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+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) {
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+ return;
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+ }
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+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0,
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+ fsl_imx8mm_memmap[FSL_IMX8MM_PCIE_PHY1].addr);
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+
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/* Unimplemented devices */
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for (i = 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) {
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switch (i) {
@@ -395,6 +423,8 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
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case FSL_IMX8MM_CCM:
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case FSL_IMX8MM_GIC_DIST:
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case FSL_IMX8MM_GIC_REDIST:
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+ case FSL_IMX8MM_PCIE1:
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+ case FSL_IMX8MM_PCIE_PHY1:
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case FSL_IMX8MM_RAM:
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case FSL_IMX8MM_OCRAM:
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case FSL_IMX8MM_SNVS_HP:
include/hw/arm/fsl-imx8mm.h
+10
@@ -16,6 +16,8 @@
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#include "hw/misc/imx7_snvs.h"
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#include "hw/misc/imx8mp_analog.h"
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#include "hw/misc/imx8mp_ccm.h"
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+#include "hw/pci-host/designware.h"
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+#include "hw/pci-host/fsl_imx8m_phy.h"
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#include "hw/sd/sdhci.h"
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#include "qom/object.h"
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#include "qemu/units.h"
@@ -44,6 +46,8 @@ struct FslImx8mmState {
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IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];
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MemoryRegion ocram;
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SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];
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+ DesignwarePCIEHost pcie;
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+ FslImx8mPciePhyState pcie_phy;
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};
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enum FslImx8mmMemoryRegions {
@@ -166,6 +170,12 @@ enum FslImx8mmIrqs {
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FSL_IMX8MM_UART2_IRQ = 27,
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FSL_IMX8MM_UART3_IRQ = 28,
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FSL_IMX8MM_UART4_IRQ = 29,
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+
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+ FSL_IMX8MM_PCI_INTA_IRQ = 122,
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+ FSL_IMX8MM_PCI_INTB_IRQ = 123,
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+ FSL_IMX8MM_PCI_INTC_IRQ = 124,
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+ FSL_IMX8MM_PCI_INTD_IRQ = 125,
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+ FSL_IMX8MM_PCI_MSI_IRQ = 127,
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};
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#endif /* FSL_IMX8MM_H */