target/riscv: Register target_get_monitor_def in SysemuCPUOps
Rename target_get_monitor_def() as riscv_monitor_get_register_legacy() and register it as SysemuCPUOps::monitor_get_register() handler. Take care to sign-extend values for 32-bit HARTs. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20260427080738.77138-21-philmd@linaro.org>
Philippe Mathieu-Daudé committed
Mar 20, 2026 at 14:17 UTC
ec15eda346ad662e1f03b4b5fe7e5e63bb284745
3 files changed
+11
-4
target/riscv/cpu.c
+1
@@ -2733,6 +2733,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
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.get_phys_page_debug = riscv_cpu_get_phys_page_debug,
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.write_elf64_note = riscv_cpu_write_elf64_note,
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.write_elf32_note = riscv_cpu_write_elf32_note,
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+ .monitor_get_register = riscv_monitor_get_register_legacy,
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.legacy_vmsd = &vmstate_riscv_cpu,
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};
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#endif
target/riscv/internals.h
+3
@@ -250,4 +250,7 @@ static inline int insn_len(uint16_t first_word)
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return (first_word & 3) == 3 ? 4 : 2;
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}
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+int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
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+ int64_t *pval);
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+
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#endif
target/riscv/monitor.c
+7
-4
@@ -27,6 +27,7 @@
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#include "monitor/hmp.h"
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#include "monitor/hmp-target.h"
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#include "system/memory.h"
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+#include "internals.h"
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#ifdef TARGET_RISCV64
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#define PTE_HEADER_FIELDS "vaddr paddr "\
@@ -311,16 +312,18 @@ static bool reg_is_vreg(const char *name)
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return false;
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}
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-int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
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+int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
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+ int64_t *pval)
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{
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- CPURISCVState *env = &RISCV_CPU(cs)->env;
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+ RISCVCPU *hart = RISCV_CPU(cs);
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+ CPURISCVState *env = cpu_env(cs);
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target_ulong val = 0;
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uint64_t val64 = 0;
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int i;
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if (reg_is_ulong_integer(env, name, &val, false) ||
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reg_is_ulong_integer(env, name, &val, true)) {
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- *pval = val;
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+ *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
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return 0;
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}
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@@ -369,7 +372,7 @@ int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
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* to do the filtering of the registers that are present.
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*/
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if (res == RISCV_EXCP_NONE) {
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- *pval = val;
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+ *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
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return 0;
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}
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}