@samitouri / QOSamiQemu / commits / ec751ce6a6

target/riscv: rvv: Support Zvfbfa vector bf16 operations

According to the Zvfbfa ISA spec v0.1, the following vector floating point instructions have different behaviors depend on the ALTFMT and VSEW fields of VTYPE CSR. When altfmt=1 and SEW=8, all vector floating-point instructions become reserved, except for the following, which are redefined to use the BF16 format for any operand that would otherwise have used the FP16 format: - vfwcvt.f.x[u].v, vfncvt.x[u].f.w, vfncvt.rtz.x[u].f.w When altfmt=1 and SEW=16, all vector floating-point instructions become reserved, except for the following, which are redefined to use the BF16 format for any operand that would otherwise have used the FP16 format: - vfadd.v[vf], vfsub.v[vf], vfmin.v[vf], vfmax.v[vf], vmfeq.v[vf], vmfle.v[vf], vmflt.v[vf], vmfne.v[vf], vmfgt.vf, vmfge.vf, vfmul.v[vf], vfrsub.vf, vfmadd.v[vf], vfnmadd.v[vf], vfmsub.v[vf], vfnmsub.v[vf], vfmacc.v[vf], vfnmacc.v[vf], vfmsac.v[vf], vfnmsac.v[vf], vfwadd.v[vf], vfwsub.v[vf], vfwadd.w[vf], vfwsub.w[vf], vfwmul.v[vf], vfwmacc.v[vf], vfwnmacc.v[vf], vfwmsac.v[vf], vfwnmsac.v[vf], vfwcvt.f.f.v, vfncvt.f.f.w, vfncvt.rod.f.f.w, vfrsqrt7.v, vfrec7.v, vfclass.v The following instructions marked with * have the same semantics regardless of altfmt. *- vfmv.f.s, vfwmaccbf16.v[vf] (only if Zvfbfwma is implemented) vfwcvtbf16.f.f.v (only if Zvfbfmin is implemented) vfncvtbf16.f.f.w (only if Zvfbfmin is implemented) The following instructions marked with ** differ only in that improperly NaN-boxed f-register operands must substitute the BF16 canonical NaN instead of the FP16 canonical NaN. **- vfsgnj.v[vf], vfsgnjn.v[vf], vfsgnjx.v[vf], vfslide1up.vf, vfslide1down.vf, vfmv.v.f, vfmerge.vfm, vfmv.s.f Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20260402125234.1371897-9-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Max Chou committed Apr 2, 2026 at 20:52 UTC ec751ce6a6f4291ef3604e9ddf0285c51602b7d5
4 files changed +989 -371
target/riscv/helper.h
+60
@@ -768,45 +768,60 @@ DEF_HELPER_6(vnclip_wx_b, void, ptr, ptr, tl, ptr, env, i32)
768 DEF_HELPER_6(vnclip_wx_h, void, ptr, ptr, tl, ptr, env, i32)
769 DEF_HELPER_6(vnclip_wx_w, void, ptr, ptr, tl, ptr, env, i32)
770
771 +DEF_HELPER_6(vfadd_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
772 DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
773 DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
774 DEF_HELPER_6(vfadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
775 +DEF_HELPER_6(vfsub_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
776 DEF_HELPER_6(vfsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
777 DEF_HELPER_6(vfsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
778 DEF_HELPER_6(vfsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
779 +DEF_HELPER_6(vfadd_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
780 DEF_HELPER_6(vfadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
781 DEF_HELPER_6(vfadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
782 DEF_HELPER_6(vfadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
783 +DEF_HELPER_6(vfsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
784 DEF_HELPER_6(vfsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
785 DEF_HELPER_6(vfsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
786 DEF_HELPER_6(vfsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
787 +DEF_HELPER_6(vfrsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
788 DEF_HELPER_6(vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
789 DEF_HELPER_6(vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
790 DEF_HELPER_6(vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
791
792 +DEF_HELPER_6(vfwadd_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
793 DEF_HELPER_6(vfwadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
794 DEF_HELPER_6(vfwadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
795 +DEF_HELPER_6(vfwsub_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
796 DEF_HELPER_6(vfwsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
797 DEF_HELPER_6(vfwsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
798 +DEF_HELPER_6(vfwadd_wv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
799 DEF_HELPER_6(vfwadd_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
800 DEF_HELPER_6(vfwadd_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
801 +DEF_HELPER_6(vfwsub_wv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
802 DEF_HELPER_6(vfwsub_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
803 DEF_HELPER_6(vfwsub_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
804 +DEF_HELPER_6(vfwadd_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
805 DEF_HELPER_6(vfwadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
806 DEF_HELPER_6(vfwadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
807 +DEF_HELPER_6(vfwsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
808 DEF_HELPER_6(vfwsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
809 DEF_HELPER_6(vfwsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
810 +DEF_HELPER_6(vfwadd_wf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
811 DEF_HELPER_6(vfwadd_wf_h, void, ptr, ptr, i64, ptr, env, i32)
812 DEF_HELPER_6(vfwadd_wf_w, void, ptr, ptr, i64, ptr, env, i32)
813 +DEF_HELPER_6(vfwsub_wf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
814 DEF_HELPER_6(vfwsub_wf_h, void, ptr, ptr, i64, ptr, env, i32)
815 DEF_HELPER_6(vfwsub_wf_w, void, ptr, ptr, i64, ptr, env, i32)
816
817 +DEF_HELPER_6(vfmul_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
818 DEF_HELPER_6(vfmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
819 DEF_HELPER_6(vfmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
820 DEF_HELPER_6(vfmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
821 DEF_HELPER_6(vfdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
822 DEF_HELPER_6(vfdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
823 DEF_HELPER_6(vfdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
824 +DEF_HELPER_6(vfmul_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
825 DEF_HELPER_6(vfmul_vf_h, void, ptr, ptr, i64, ptr, env, i32)
826 DEF_HELPER_6(vfmul_vf_w, void, ptr, ptr, i64, ptr, env, i32)
827 DEF_HELPER_6(vfmul_vf_d, void, ptr, ptr, i64, ptr, env, i32)
@@ -817,74 +832,98 @@ DEF_HELPER_6(vfrdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32)
832 DEF_HELPER_6(vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32)
833 DEF_HELPER_6(vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
834
835 +DEF_HELPER_6(vfwmul_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
836 DEF_HELPER_6(vfwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
837 DEF_HELPER_6(vfwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
838 +DEF_HELPER_6(vfwmul_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
839 DEF_HELPER_6(vfwmul_vf_h, void, ptr, ptr, i64, ptr, env, i32)
840 DEF_HELPER_6(vfwmul_vf_w, void, ptr, ptr, i64, ptr, env, i32)
841
842 +DEF_HELPER_6(vfmacc_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
843 DEF_HELPER_6(vfmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
844 DEF_HELPER_6(vfmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
845 DEF_HELPER_6(vfmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
846 +DEF_HELPER_6(vfnmacc_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
847 DEF_HELPER_6(vfnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
848 DEF_HELPER_6(vfnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
849 DEF_HELPER_6(vfnmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
850 +DEF_HELPER_6(vfmsac_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
851 DEF_HELPER_6(vfmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
852 DEF_HELPER_6(vfmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
853 DEF_HELPER_6(vfmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
854 +DEF_HELPER_6(vfnmsac_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
855 DEF_HELPER_6(vfnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
856 DEF_HELPER_6(vfnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
857 DEF_HELPER_6(vfnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
858 +DEF_HELPER_6(vfmadd_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
859 DEF_HELPER_6(vfmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
860 DEF_HELPER_6(vfmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
861 DEF_HELPER_6(vfmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
862 +DEF_HELPER_6(vfnmadd_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
863 DEF_HELPER_6(vfnmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
864 DEF_HELPER_6(vfnmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
865 DEF_HELPER_6(vfnmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
866 +DEF_HELPER_6(vfmsub_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
867 DEF_HELPER_6(vfmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
868 DEF_HELPER_6(vfmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
869 DEF_HELPER_6(vfmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
870 +DEF_HELPER_6(vfnmsub_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
871 DEF_HELPER_6(vfnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
872 DEF_HELPER_6(vfnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
873 DEF_HELPER_6(vfnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
874 +DEF_HELPER_6(vfmacc_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
875 DEF_HELPER_6(vfmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
876 DEF_HELPER_6(vfmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
877 DEF_HELPER_6(vfmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32)
878 +DEF_HELPER_6(vfnmacc_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
879 DEF_HELPER_6(vfnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
880 DEF_HELPER_6(vfnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
881 DEF_HELPER_6(vfnmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32)
882 +DEF_HELPER_6(vfmsac_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
883 DEF_HELPER_6(vfmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
884 DEF_HELPER_6(vfmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
885 DEF_HELPER_6(vfmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32)
886 +DEF_HELPER_6(vfnmsac_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
887 DEF_HELPER_6(vfnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
888 DEF_HELPER_6(vfnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
889 DEF_HELPER_6(vfnmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32)
890 +DEF_HELPER_6(vfmadd_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
891 DEF_HELPER_6(vfmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
892 DEF_HELPER_6(vfmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
893 DEF_HELPER_6(vfmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
894 +DEF_HELPER_6(vfnmadd_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
895 DEF_HELPER_6(vfnmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
896 DEF_HELPER_6(vfnmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
897 DEF_HELPER_6(vfnmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
898 +DEF_HELPER_6(vfmsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
899 DEF_HELPER_6(vfmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
900 DEF_HELPER_6(vfmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
901 DEF_HELPER_6(vfmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
902 +DEF_HELPER_6(vfnmsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
903 DEF_HELPER_6(vfnmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
904 DEF_HELPER_6(vfnmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
905 DEF_HELPER_6(vfnmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
906
907 DEF_HELPER_6(vfwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
908 DEF_HELPER_6(vfwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
909 +DEF_HELPER_6(vfwnmacc_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
910 DEF_HELPER_6(vfwnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
911 DEF_HELPER_6(vfwnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
912 +DEF_HELPER_6(vfwmsac_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
913 DEF_HELPER_6(vfwmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
914 DEF_HELPER_6(vfwmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
915 +DEF_HELPER_6(vfwnmsac_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
916 DEF_HELPER_6(vfwnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
917 DEF_HELPER_6(vfwnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
918 DEF_HELPER_6(vfwmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
919 DEF_HELPER_6(vfwmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
920 +DEF_HELPER_6(vfwnmacc_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
921 DEF_HELPER_6(vfwnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
922 DEF_HELPER_6(vfwnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
923 +DEF_HELPER_6(vfwmsac_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
924 DEF_HELPER_6(vfwmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
925 DEF_HELPER_6(vfwmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
926 +DEF_HELPER_6(vfwnmsac_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
927 DEF_HELPER_6(vfwnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
928 DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
929
@@ -892,23 +931,29 @@ DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32)
931 DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32)
932 DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32)
933
934 +DEF_HELPER_5(vfrsqrt7_v_h_bf16, void, ptr, ptr, ptr, env, i32)
935 DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32)
936 DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32)
937 DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32)
938
939 +DEF_HELPER_5(vfrec7_v_h_bf16, void, ptr, ptr, ptr, env, i32)
940 DEF_HELPER_5(vfrec7_v_h, void, ptr, ptr, ptr, env, i32)
941 DEF_HELPER_5(vfrec7_v_w, void, ptr, ptr, ptr, env, i32)
942 DEF_HELPER_5(vfrec7_v_d, void, ptr, ptr, ptr, env, i32)
943
944 +DEF_HELPER_6(vfmin_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
945 DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
946 DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
947 DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
948 +DEF_HELPER_6(vfmax_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
949 DEF_HELPER_6(vfmax_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
950 DEF_HELPER_6(vfmax_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
951 DEF_HELPER_6(vfmax_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
952 +DEF_HELPER_6(vfmin_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
953 DEF_HELPER_6(vfmin_vf_h, void, ptr, ptr, i64, ptr, env, i32)
954 DEF_HELPER_6(vfmin_vf_w, void, ptr, ptr, i64, ptr, env, i32)
955 DEF_HELPER_6(vfmin_vf_d, void, ptr, ptr, i64, ptr, env, i32)
956 +DEF_HELPER_6(vfmax_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
957 DEF_HELPER_6(vfmax_vf_h, void, ptr, ptr, i64, ptr, env, i32)
958 DEF_HELPER_6(vfmax_vf_w, void, ptr, ptr, i64, ptr, env, i32)
959 DEF_HELPER_6(vfmax_vf_d, void, ptr, ptr, i64, ptr, env, i32)
@@ -932,37 +977,48 @@ DEF_HELPER_6(vfsgnjx_vf_h, void, ptr, ptr, i64, ptr, env, i32)
977 DEF_HELPER_6(vfsgnjx_vf_w, void, ptr, ptr, i64, ptr, env, i32)
978 DEF_HELPER_6(vfsgnjx_vf_d, void, ptr, ptr, i64, ptr, env, i32)
979
980 +DEF_HELPER_6(vmfeq_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
981 DEF_HELPER_6(vmfeq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
982 DEF_HELPER_6(vmfeq_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
983 DEF_HELPER_6(vmfeq_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
984 +DEF_HELPER_6(vmfne_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
985 DEF_HELPER_6(vmfne_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
986 DEF_HELPER_6(vmfne_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
987 DEF_HELPER_6(vmfne_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
988 +DEF_HELPER_6(vmflt_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
989 DEF_HELPER_6(vmflt_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
990 DEF_HELPER_6(vmflt_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
991 DEF_HELPER_6(vmflt_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
992 +DEF_HELPER_6(vmfle_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32)
993 DEF_HELPER_6(vmfle_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
994 DEF_HELPER_6(vmfle_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
995 DEF_HELPER_6(vmfle_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
996 +DEF_HELPER_6(vmfeq_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
997 DEF_HELPER_6(vmfeq_vf_h, void, ptr, ptr, i64, ptr, env, i32)
998 DEF_HELPER_6(vmfeq_vf_w, void, ptr, ptr, i64, ptr, env, i32)
999 DEF_HELPER_6(vmfeq_vf_d, void, ptr, ptr, i64, ptr, env, i32)
1000 +DEF_HELPER_6(vmfne_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
1001 DEF_HELPER_6(vmfne_vf_h, void, ptr, ptr, i64, ptr, env, i32)
1002 DEF_HELPER_6(vmfne_vf_w, void, ptr, ptr, i64, ptr, env, i32)
1003 DEF_HELPER_6(vmfne_vf_d, void, ptr, ptr, i64, ptr, env, i32)
1004 +DEF_HELPER_6(vmflt_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
1005 DEF_HELPER_6(vmflt_vf_h, void, ptr, ptr, i64, ptr, env, i32)
1006 DEF_HELPER_6(vmflt_vf_w, void, ptr, ptr, i64, ptr, env, i32)
1007 DEF_HELPER_6(vmflt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
1008 +DEF_HELPER_6(vmfle_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
1009 DEF_HELPER_6(vmfle_vf_h, void, ptr, ptr, i64, ptr, env, i32)
1010 DEF_HELPER_6(vmfle_vf_w, void, ptr, ptr, i64, ptr, env, i32)
1011 DEF_HELPER_6(vmfle_vf_d, void, ptr, ptr, i64, ptr, env, i32)
1012 +DEF_HELPER_6(vmfgt_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
1013 DEF_HELPER_6(vmfgt_vf_h, void, ptr, ptr, i64, ptr, env, i32)
1014 DEF_HELPER_6(vmfgt_vf_w, void, ptr, ptr, i64, ptr, env, i32)
1015 DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
1016 +DEF_HELPER_6(vmfge_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32)
1017 DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
1018 DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
1019 DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
1020
1021 +DEF_HELPER_5(vfclass_v_h_bf16, void, ptr, ptr, ptr, env, i32)
1022 DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
1023 DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
1024 DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
@@ -989,18 +1045,22 @@ DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
1045 DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
1046 DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
1047 DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32)
1048 +DEF_HELPER_5(vfwcvt_f_xu_v_b_bf16, void, ptr, ptr, ptr, env, i32)
1049 DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
1050 DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
1051 DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32)
1052 +DEF_HELPER_5(vfwcvt_f_x_v_b_bf16, void, ptr, ptr, ptr, env, i32)
1053 DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
1054 DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
1055 DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
1056 DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
1057
1058 DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
1059 +DEF_HELPER_5(vfncvt_xu_f_w_b_bf16, void, ptr, ptr, ptr, env, i32)
1060 DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32)
1061 DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32)
1062 DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32)
1063 +DEF_HELPER_5(vfncvt_x_f_w_b_bf16, void, ptr, ptr, ptr, env, i32)
1064 DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32)
1065 DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32)
1066 DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32)
target/riscv/insn_trans/trans_rvv.c.inc
+599 -371
@@ -40,6 +40,9 @@ static bool require_rvf(DisasContext *s)
40
41 switch (s->sew) {
42 case MO_16:
43 + if (s->altfmt) {
44 + return s->cfg_ptr->ext_zvfbfa;
45 + }
46 return s->cfg_ptr->ext_zvfh;
47 case MO_32:
48 return s->cfg_ptr->ext_zve32f;
@@ -58,6 +61,9 @@ static bool require_rvfmin(DisasContext *s)
61
62 switch (s->sew) {
63 case MO_16:
64 + if (s->altfmt) {
65 + return s->cfg_ptr->ext_zvfbfa;
66 + }
67 return s->cfg_ptr->ext_zvfhmin;
68 case MO_32:
69 return s->cfg_ptr->ext_zve32f;
@@ -74,6 +80,9 @@ static bool require_scale_rvf(DisasContext *s)
80
81 switch (s->sew) {
82 case MO_8:
83 + if (s->altfmt) {
84 + return s->cfg_ptr->ext_zvfbfa;
85 + }
86 return s->cfg_ptr->ext_zvfh;
87 case MO_16:
88 return s->cfg_ptr->ext_zve32f;
@@ -2334,25 +2343,39 @@ static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
2343 }
2344 }
2345
2346 +/*
2347 + * Check altfmt & sew combinations when Zvfbfa extension is enabled.
2348 + */
2349 +static bool vext_check_altfmt(DisasContext *s, int8_t valid_vsew)
2350 +{
2351 + if (s->cfg_ptr->ext_zvfbfa) {
2352 + if (s->altfmt && (valid_vsew == -1 || s->sew != valid_vsew)) {
2353 + return false;
2354 + }
2355 + }
2356 + return true;
2357 +}
2358 +
2359 /* Vector Single-Width Floating-Point Add/Subtract Instructions */
2360
2361 /*
2362 * If the current SEW does not correspond to a supported IEEE floating-point
2363 * type, an illegal instruction exception is raised.
2364 */
2343 -static bool opfvv_check(DisasContext *s, arg_rmrr *a)
2365 +static bool opfvv_check(DisasContext *s, arg_rmrr *a, int8_t valid_bfa_vsew)
2366 {
2367 return require_rvv(s) &&
2368 require_rvf(s) &&
2369 vext_check_isa_ill(s) &&
2348 - vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
2370 + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
2371 + vext_check_altfmt(s, valid_bfa_vsew);
2372 }
2373
2374 /* OPFVV without GVEC IR */
2375 #define GEN_OPFVV_TRANS(NAME, CHECK) \
2376 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2377 { \
2355 - if (CHECK(s, a)) { \
2378 + if (CHECK(s, a, -1)) { \
2379 uint32_t data = 0; \
2380 static gen_helper_gvec_4_ptr * const fns[3] = { \
2381 gen_helper_##NAME##_h, \
@@ -2378,8 +2401,41 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2401 } \
2402 return false; \
2403 }
2381 -GEN_OPFVV_TRANS(vfadd_vv, opfvv_check)
2382 -GEN_OPFVV_TRANS(vfsub_vv, opfvv_check)
2404 +
2405 +#define GEN_OPFVV_BFA_TRANS(NAME, CHECK, BFA_HELPER) \
2406 +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2407 +{ \
2408 + if (CHECK(s, a, MO_16)) { \
2409 + uint32_t data = 0; \
2410 + static gen_helper_gvec_4_ptr * const fns[3] = { \
2411 + gen_helper_##NAME##_h, \
2412 + gen_helper_##NAME##_w, \
2413 + gen_helper_##NAME##_d \
2414 + }; \
2415 + gen_set_rm(s, RISCV_FRM_DYN); \
2416 + \
2417 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
2418 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2419 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2420 + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
2421 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2422 + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2423 + vreg_ofs(s, a->rs1), \
2424 + vreg_ofs(s, a->rs2), tcg_env, \
2425 + s->cfg_ptr->vlenb, \
2426 + s->cfg_ptr->vlenb, data, \
2427 + (s->altfmt ? gen_helper_##BFA_HELPER : \
2428 + fns[s->sew - 1])); \
2429 + tcg_gen_movi_tl(cpu_vstart, 0); \
2430 + finalize_rvv_inst(s); \
2431 + \
2432 + return true; \
2433 + } \
2434 + return false; \
2435 +}
2436 +
2437 +GEN_OPFVV_BFA_TRANS(vfadd_vv, opfvv_check, vfadd_vv_h_bf16)
2438 +GEN_OPFVV_BFA_TRANS(vfsub_vv, opfvv_check, vfsub_vv_h_bf16)
2439
2440 typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr,
2441 TCGv_env, TCGv_i32);
@@ -2415,244 +2471,316 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
2471 * If the current SEW does not correspond to a supported IEEE floating-point
2472 * type, an illegal instruction exception is raised
2473 */
2418 -static bool opfvf_check(DisasContext *s, arg_rmrr *a)
2474 +static bool opfvf_check(DisasContext *s, arg_rmrr *a, int8_t valid_bfa_vsew)
2475 {
2476 return require_rvv(s) &&
2477 require_rvf(s) &&
2478 vext_check_isa_ill(s) &&
2423 - vext_check_ss(s, a->rd, a->rs2, a->vm);
2479 + vext_check_ss(s, a->rd, a->rs2, a->vm) &&
2480 + vext_check_altfmt(s, valid_bfa_vsew);
2481 }
2482
2483 /* OPFVF without GVEC IR */
2427 -#define GEN_OPFVF_TRANS(NAME, CHECK) \
2428 -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2429 -{ \
2430 - if (CHECK(s, a)) { \
2431 - uint32_t data = 0; \
2432 - static gen_helper_opfvf *const fns[3] = { \
2433 - gen_helper_##NAME##_h, \
2434 - gen_helper_##NAME##_w, \
2435 - gen_helper_##NAME##_d, \
2436 - }; \
2437 - gen_set_rm(s, RISCV_FRM_DYN); \
2438 - data = FIELD_DP32(data, VDATA, VM, a->vm); \
2439 - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2440 - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2441 - data = FIELD_DP32(data, VDATA, VTA_ALL_1S, \
2442 - s->cfg_vta_all_1s); \
2443 - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2444 - return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
2445 - fns[s->sew - 1], s); \
2446 - } \
2447 - return false; \
2448 -}
2449 -
2450 -GEN_OPFVF_TRANS(vfadd_vf, opfvf_check)
2451 -GEN_OPFVF_TRANS(vfsub_vf, opfvf_check)
2452 -GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
2484 +#define GEN_OPFVF_TRANS(NAME, CHECK) \
2485 +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2486 +{ \
2487 + if (CHECK(s, a, -1)) { \
2488 + uint32_t data = 0; \
2489 + static gen_helper_opfvf *const fns[3] = { \
2490 + gen_helper_##NAME##_h, \
2491 + gen_helper_##NAME##_w, \
2492 + gen_helper_##NAME##_d, \
2493 + }; \
2494 + gen_set_rm(s, RISCV_FRM_DYN); \
2495 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
2496 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2497 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2498 + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, \
2499 + s->cfg_vta_all_1s); \
2500 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2501 + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
2502 + fns[s->sew - 1], s); \
2503 + } \
2504 + return false; \
2505 +}
2506 +
2507 +#define GEN_OPFVF_BFA_TRANS(NAME, CHECK, BFA_HELPER) \
2508 +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2509 +{ \
2510 + if (CHECK(s, a, MO_16)) { \
2511 + uint32_t data = 0; \
2512 + static gen_helper_opfvf *const fns[3] = { \
2513 + gen_helper_##NAME##_h, \
2514 + gen_helper_##NAME##_w, \
2515 + gen_helper_##NAME##_d, \
2516 + }; \
2517 + gen_set_rm(s, RISCV_FRM_DYN); \
2518 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
2519 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2520 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2521 + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, \
2522 + s->cfg_vta_all_1s); \
2523 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2524 + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
2525 + (s->altfmt ? gen_helper_##BFA_HELPER : \
2526 + fns[s->sew - 1]), \
2527 + s); \
2528 + } \
2529 + return false; \
2530 +}
2531 +
2532 +GEN_OPFVF_BFA_TRANS(vfadd_vf, opfvf_check, vfadd_vf_h_bf16)
2533 +GEN_OPFVF_BFA_TRANS(vfsub_vf, opfvf_check, vfsub_vf_h_bf16)
2534 +GEN_OPFVF_BFA_TRANS(vfrsub_vf, opfvf_check, vfrsub_vf_h_bf16)
2535
2536 /* Vector Widening Floating-Point Add/Subtract Instructions */
2455 -static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
2537 +static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a,
2538 + int8_t valid_bfa_vsew)
2539 {
2540 return require_rvv(s) &&
2541 require_rvf(s) &&
2542 require_scale_rvf(s) &&
2543 vext_check_isa_ill(s) &&
2461 - vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
2544 + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
2545 + vext_check_altfmt(s, valid_bfa_vsew);
2546 }
2547
2464 -static bool opfvv_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
2548 +static bool opfvv_overwrite_widen_check(DisasContext *s, arg_rmrr *a,
2549 + int8_t valid_bfa_vsew)
2550 {
2466 - return require_rvv(s) &&
2467 - require_rvf(s) &&
2468 - require_scale_rvf(s) &&
2469 - vext_check_isa_ill(s) &&
2470 - vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
2551 + return opfvv_widen_check(s, a, valid_bfa_vsew) &&
2552 vext_check_input_eew(s, a->rd, s->sew + 1, a->rs1, s->sew, a->vm) &&
2553 vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
2554 }
2555
2556 /* OPFVV with WIDEN */
2476 -#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \
2477 -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2478 -{ \
2479 - if (CHECK(s, a)) { \
2480 - uint32_t data = 0; \
2481 - static gen_helper_gvec_4_ptr * const fns[2] = { \
2482 - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
2483 - }; \
2484 - gen_set_rm(s, RISCV_FRM_DYN); \
2485 - \
2486 - data = FIELD_DP32(data, VDATA, VM, a->vm); \
2487 - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2488 - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2489 - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2490 - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2491 - vreg_ofs(s, a->rs1), \
2492 - vreg_ofs(s, a->rs2), tcg_env, \
2493 - s->cfg_ptr->vlenb, \
2494 - s->cfg_ptr->vlenb, data, \
2495 - fns[s->sew - 1]); \
2496 - finalize_rvv_inst(s); \
2497 - return true; \
2498 - } \
2499 - return false; \
2500 -}
2501 -
2502 -GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check)
2503 -GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
2504 -
2505 -static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
2557 +#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \
2558 +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2559 +{ \
2560 + if (CHECK(s, a, -1)) { \
2561 + uint32_t data = 0; \
2562 + static gen_helper_gvec_4_ptr * const fns[2] = { \
2563 + gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
2564 + }; \
2565 + gen_set_rm(s, RISCV_FRM_DYN); \
2566 + \
2567 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
2568 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2569 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2570 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2571 + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2572 + vreg_ofs(s, a->rs1), \
2573 + vreg_ofs(s, a->rs2), tcg_env, \
2574 + s->cfg_ptr->vlenb, \
2575 + s->cfg_ptr->vlenb, data, \
2576 + fns[s->sew - 1]); \
2577 + finalize_rvv_inst(s); \
2578 + return true; \
2579 + } \
2580 + return false; \
2581 +}
2582 +
2583 +#define GEN_OPFVV_WIDEN_BFA_TRANS(NAME, CHECK, BFA_HELPER) \
2584 +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2585 +{ \
2586 + if (CHECK(s, a, MO_16)) { \
2587 + uint32_t data = 0; \
2588 + static gen_helper_gvec_4_ptr * const fns[2] = { \
2589 + gen_helper_##NAME##_h, \
2590 + gen_helper_##NAME##_w \
2591 + }; \
2592 + gen_set_rm(s, RISCV_FRM_DYN); \
2593 + \
2594 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
2595 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2596 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2597 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2598 + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2599 + vreg_ofs(s, a->rs1), \
2600 + vreg_ofs(s, a->rs2), tcg_env, \
2601 + s->cfg_ptr->vlenb, \
2602 + s->cfg_ptr->vlenb, data, \
2603 + (s->altfmt ? gen_helper_##BFA_HELPER : \
2604 + fns[s->sew - 1])); \
2605 + finalize_rvv_inst(s); \
2606 + return true; \
2607 + } \
2608 + return false; \
2609 +}
2610 +
2611 +GEN_OPFVV_WIDEN_BFA_TRANS(vfwadd_vv, opfvv_widen_check, vfwadd_vv_h_bf16)
2612 +GEN_OPFVV_WIDEN_BFA_TRANS(vfwsub_vv, opfvv_widen_check, vfwsub_vv_h_bf16)
2613 +
2614 +static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a,
2615 + int8_t valid_bfa_vsew)
2616 {
2617 return require_rvv(s) &&
2618 require_rvf(s) &&
2619 require_scale_rvf(s) &&
2620 vext_check_isa_ill(s) &&
2511 - vext_check_ds(s, a->rd, a->rs2, a->vm);
2621 + vext_check_ds(s, a->rd, a->rs2, a->vm) &&
2622 + vext_check_altfmt(s, valid_bfa_vsew);
2623 }
2624
2514 -static bool opfvf_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
2625 +static bool opfvf_overwrite_widen_check(DisasContext *s, arg_rmrr *a,
2626 + int8_t valid_bfa_vsew)
2627 {
2516 - return require_rvv(s) &&
2517 - require_rvf(s) &&
2518 - require_scale_rvf(s) &&
2519 - vext_check_isa_ill(s) &&
2520 - vext_check_ds(s, a->rd, a->rs2, a->vm) &&
2628 + return opfvf_widen_check(s, a, valid_bfa_vsew) &&
2629 vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
2630 }
2631
2632 /* OPFVF with WIDEN */
2525 -#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \
2526 -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2527 -{ \
2528 - if (CHECK(s, a)) { \
2529 - uint32_t data = 0; \
2530 - static gen_helper_opfvf *const fns[2] = { \
2531 - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
2532 - }; \
2533 - gen_set_rm(s, RISCV_FRM_DYN); \
2534 - data = FIELD_DP32(data, VDATA, VM, a->vm); \
2535 - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2536 - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2537 - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2538 - return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
2539 - fns[s->sew - 1], s); \
2540 - } \
2541 - return false; \
2542 -}
2543 -
2544 -GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check)
2545 -GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check)
2546 -
2547 -static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
2633 +#define GEN_OPFVF_WIDEN_BFA_TRANS(NAME, CHECK, BFA_HELPER) \
2634 +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2635 +{ \
2636 + if (CHECK(s, a, MO_16)) { \
2637 + uint32_t data = 0; \
2638 + static gen_helper_opfvf *const fns[2] = { \
2639 + gen_helper_##NAME##_h, \
2640 + gen_helper_##NAME##_w, \
2641 + }; \
2642 + gen_set_rm(s, RISCV_FRM_DYN); \
2643 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
2644 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2645 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2646 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2647 + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
2648 + (s->altfmt ? gen_helper_##BFA_HELPER : \
2649 + fns[s->sew - 1]), \
2650 + s); \
2651 + } \
2652 + return false; \
2653 +}
2654 +
2655 +GEN_OPFVF_WIDEN_BFA_TRANS(vfwadd_vf, opfvf_widen_check, vfwadd_vf_h_bf16)
2656 +GEN_OPFVF_WIDEN_BFA_TRANS(vfwsub_vf, opfvf_widen_check, vfwsub_vf_h_bf16)
2657 +
2658 +static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a,
2659 + int8_t valid_bfa_vsew)
2660 {
2661 return require_rvv(s) &&
2662 require_rvf(s) &&
2663 require_scale_rvf(s) &&
2664 vext_check_isa_ill(s) &&
2553 - vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
2665 + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
2666 + vext_check_altfmt(s, valid_bfa_vsew);
2667 }
2668
2669 /* WIDEN OPFVV with WIDEN */
2557 -#define GEN_OPFWV_WIDEN_TRANS(NAME) \
2558 -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2559 -{ \
2560 - if (opfwv_widen_check(s, a)) { \
2561 - uint32_t data = 0; \
2562 - static gen_helper_gvec_4_ptr * const fns[2] = { \
2563 - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
2564 - }; \
2565 - gen_set_rm(s, RISCV_FRM_DYN); \
2566 - \
2567 - data = FIELD_DP32(data, VDATA, VM, a->vm); \
2568 - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2569 - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2570 - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2571 - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2572 - vreg_ofs(s, a->rs1), \
2573 - vreg_ofs(s, a->rs2), tcg_env, \
2574 - s->cfg_ptr->vlenb, \
2575 - s->cfg_ptr->vlenb, data, \
2576 - fns[s->sew - 1]); \
2577 - finalize_rvv_inst(s); \
2578 - return true; \
2579 - } \
2580 - return false; \
2670 +#define GEN_OPFWV_WIDEN_BFA_TRANS(NAME) \
2671 +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2672 +{ \
2673 + if (opfwv_widen_check(s, a, MO_16)) { \
2674 + uint32_t data = 0; \
2675 + static gen_helper_gvec_4_ptr * const fns[2] = { \
2676 + gen_helper_##NAME##_h, \
2677 + gen_helper_##NAME##_w \
2678 + }; \
2679 + gen_set_rm(s, RISCV_FRM_DYN); \
2680 + \
2681 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
2682 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2683 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2684 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2685 + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2686 + vreg_ofs(s, a->rs1), \
2687 + vreg_ofs(s, a->rs2), tcg_env, \
2688 + s->cfg_ptr->vlenb, \
2689 + s->cfg_ptr->vlenb, data, \
2690 + (s->altfmt ? gen_helper_##NAME##_h_bf16 : \
2691 + fns[s->sew - 1])); \
2692 + finalize_rvv_inst(s); \
2693 + return true; \
2694 + } \
2695 + return false; \
2696 }
2697
2583 -GEN_OPFWV_WIDEN_TRANS(vfwadd_wv)
2584 -GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
2698 +GEN_OPFWV_WIDEN_BFA_TRANS(vfwadd_wv)
2699 +GEN_OPFWV_WIDEN_BFA_TRANS(vfwsub_wv)
2700
2586 -static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
2701 +static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a,
2702 + int8_t valid_bfa_vsew)
2703 {
2704 return require_rvv(s) &&
2705 require_rvf(s) &&
2706 require_scale_rvf(s) &&
2707 vext_check_isa_ill(s) &&
2592 - vext_check_dd(s, a->rd, a->rs2, a->vm);
2708 + vext_check_dd(s, a->rd, a->rs2, a->vm) &&
2709 + vext_check_altfmt(s, valid_bfa_vsew);
2710 }
2711
2712 /* WIDEN OPFVF with WIDEN */
2596 -#define GEN_OPFWF_WIDEN_TRANS(NAME) \
2597 -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2598 -{ \
2599 - if (opfwf_widen_check(s, a)) { \
2600 - uint32_t data = 0; \
2601 - static gen_helper_opfvf *const fns[2] = { \
2602 - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
2603 - }; \
2604 - gen_set_rm(s, RISCV_FRM_DYN); \
2605 - data = FIELD_DP32(data, VDATA, VM, a->vm); \
2606 - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2607 - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2608 - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2609 - return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
2610 - fns[s->sew - 1], s); \
2611 - } \
2612 - return false; \
2613 -}
2614 -
2615 -GEN_OPFWF_WIDEN_TRANS(vfwadd_wf)
2616 -GEN_OPFWF_WIDEN_TRANS(vfwsub_wf)
2713 +#define GEN_OPFWF_WIDEN_BFA_TRANS(NAME) \
2714 +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
2715 +{ \
2716 + if (opfwf_widen_check(s, a, MO_16)) { \
2717 + uint32_t data = 0; \
2718 + static gen_helper_opfvf *const fns[2] = { \
2719 + gen_helper_##NAME##_h, \
2720 + gen_helper_##NAME##_w \
2721 + }; \
2722 + gen_set_rm(s, RISCV_FRM_DYN); \
2723 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
2724 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2725 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2726 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2727 + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
2728 + (s->altfmt ? gen_helper_##NAME##_h_bf16 : \
2729 + fns[s->sew - 1]), \
2730 + s); \
2731 + } \
2732 + return false; \
2733 +}
2734 +
2735 +GEN_OPFWF_WIDEN_BFA_TRANS(vfwadd_wf)
2736 +GEN_OPFWF_WIDEN_BFA_TRANS(vfwsub_wf)
2737
2738 /* Vector Single-Width Floating-Point Multiply/Divide Instructions */
2619 -GEN_OPFVV_TRANS(vfmul_vv, opfvv_check)
2739 +GEN_OPFVV_BFA_TRANS(vfmul_vv, opfvv_check, vfmul_vv_h_bf16)
2740 GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
2621 -GEN_OPFVF_TRANS(vfmul_vf, opfvf_check)
2741 +GEN_OPFVF_BFA_TRANS(vfmul_vf, opfvf_check, vfmul_vf_h_bf16)
2742 GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check)
2743 GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
2744
2745 /* Vector Widening Floating-Point Multiply */
2626 -GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
2627 -GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check)
2746 +GEN_OPFVV_WIDEN_BFA_TRANS(vfwmul_vv, opfvv_widen_check, vfwmul_vv_h_bf16)
2747 +GEN_OPFVF_WIDEN_BFA_TRANS(vfwmul_vf, opfvf_widen_check, vfwmul_vf_h_bf16)
2748
2749 /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
2630 -GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
2631 -GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check)
2632 -GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check)
2633 -GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check)
2634 -GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check)
2635 -GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check)
2636 -GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check)
2637 -GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check)
2638 -GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check)
2639 -GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check)
2640 -GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check)
2641 -GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check)
2642 -GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check)
2643 -GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check)
2644 -GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
2645 -GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
2750 +GEN_OPFVV_BFA_TRANS(vfmacc_vv, opfvv_check, vfmacc_vv_h_bf16)
2751 +GEN_OPFVV_BFA_TRANS(vfnmacc_vv, opfvv_check, vfnmacc_vv_h_bf16)
2752 +GEN_OPFVV_BFA_TRANS(vfmsac_vv, opfvv_check, vfmsac_vv_h_bf16)
2753 +GEN_OPFVV_BFA_TRANS(vfnmsac_vv, opfvv_check, vfnmsac_vv_h_bf16)
2754 +GEN_OPFVV_BFA_TRANS(vfmadd_vv, opfvv_check, vfmadd_vv_h_bf16)
2755 +GEN_OPFVV_BFA_TRANS(vfnmadd_vv, opfvv_check, vfnmadd_vv_h_bf16)
2756 +GEN_OPFVV_BFA_TRANS(vfmsub_vv, opfvv_check, vfmsub_vv_h_bf16)
2757 +GEN_OPFVV_BFA_TRANS(vfnmsub_vv, opfvv_check, vfnmsub_vv_h_bf16)
2758 +GEN_OPFVF_BFA_TRANS(vfmacc_vf, opfvf_check, vfmacc_vf_h_bf16)
2759 +GEN_OPFVF_BFA_TRANS(vfnmacc_vf, opfvf_check, vfnmacc_vf_h_bf16)
2760 +GEN_OPFVF_BFA_TRANS(vfmsac_vf, opfvf_check, vfmsac_vf_h_bf16)
2761 +GEN_OPFVF_BFA_TRANS(vfnmsac_vf, opfvf_check, vfnmsac_vf_h_bf16)
2762 +GEN_OPFVF_BFA_TRANS(vfmadd_vf, opfvf_check, vfmadd_vf_h_bf16)
2763 +GEN_OPFVF_BFA_TRANS(vfnmadd_vf, opfvf_check, vfnmadd_vf_h_bf16)
2764 +GEN_OPFVF_BFA_TRANS(vfmsub_vf, opfvf_check, vfmsub_vf_h_bf16)
2765 +GEN_OPFVF_BFA_TRANS(vfnmsub_vf, opfvf_check, vfnmsub_vf_h_bf16)
2766
2767 /* Vector Widening Floating-Point Fused Multiply-Add Instructions */
2648 -GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_overwrite_widen_check)
2649 -GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_overwrite_widen_check)
2650 -GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_overwrite_widen_check)
2651 -GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_overwrite_widen_check)
2652 -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_overwrite_widen_check)
2653 -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_overwrite_widen_check)
2654 -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_overwrite_widen_check)
2655 -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_overwrite_widen_check)
2768 +GEN_OPFVV_WIDEN_BFA_TRANS(vfwmacc_vv, opfvv_overwrite_widen_check,
2769 + vfwmaccbf16_vv)
2770 +GEN_OPFVV_WIDEN_BFA_TRANS(vfwnmacc_vv, opfvv_overwrite_widen_check,
2771 + vfwnmacc_vv_h_bf16)
2772 +GEN_OPFVV_WIDEN_BFA_TRANS(vfwmsac_vv, opfvv_overwrite_widen_check,
2773 + vfwmsac_vv_h_bf16)
2774 +GEN_OPFVV_WIDEN_BFA_TRANS(vfwnmsac_vv, opfvv_overwrite_widen_check,
2775 + vfwnmsac_vv_h_bf16)
2776 +GEN_OPFVF_WIDEN_BFA_TRANS(vfwmacc_vf, opfvf_overwrite_widen_check,
2777 + vfwmaccbf16_vf)
2778 +GEN_OPFVF_WIDEN_BFA_TRANS(vfwnmacc_vf, opfvf_overwrite_widen_check,
2779 + vfwnmacc_vf_h_bf16)
2780 +GEN_OPFVF_WIDEN_BFA_TRANS(vfwmsac_vf, opfvf_overwrite_widen_check,
2781 + vfwmsac_vf_h_bf16)
2782 +GEN_OPFVF_WIDEN_BFA_TRANS(vfwnmsac_vf, opfvf_overwrite_widen_check,
2783 + vfwnmsac_vf_h_bf16)
2784
2785 /* Vector Floating-Point Square-Root Instruction */
2786
@@ -2660,21 +2788,23 @@ GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_overwrite_widen_check)
2788 * If the current SEW does not correspond to a supported IEEE floating-point
2789 * type, an illegal instruction exception is raised
2790 */
2663 -static bool opfv_check(DisasContext *s, arg_rmr *a)
2791 +static bool opfv_check(DisasContext *s, arg_rmr *a, int8_t valid_bfa_vsew)
2792 {
2793 return require_rvv(s) &&
2794 require_rvf(s) &&
2795 vext_check_isa_ill(s) &&
2796 /* OPFV instructions ignore vs1 check */
2669 - vext_check_ss(s, a->rd, a->rs2, a->vm);
2797 + vext_check_ss(s, a->rd, a->rs2, a->vm) &&
2798 + vext_check_altfmt(s, valid_bfa_vsew);
2799 }
2800
2801 static bool do_opfv(DisasContext *s, arg_rmr *a,
2802 gen_helper_gvec_3_ptr *fn,
2674 - bool (*checkfn)(DisasContext *, arg_rmr *),
2675 - int rm)
2803 + bool (*checkfn)(DisasContext *, arg_rmr *, int8_t),
2804 + int rm,
2805 + int8_t valid_bfa_vsew)
2806 {
2677 - if (checkfn(s, a)) {
2807 + if (checkfn(s, a, valid_bfa_vsew)) {
2808 uint32_t data = 0;
2809 gen_set_rm_chkfrm(s, rm);
2810
@@ -2692,76 +2822,95 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
2822 return false;
2823 }
2824
2695 -#define GEN_OPFV_TRANS(NAME, CHECK, FRM) \
2696 -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2697 -{ \
2698 - static gen_helper_gvec_3_ptr * const fns[3] = { \
2699 - gen_helper_##NAME##_h, \
2700 - gen_helper_##NAME##_w, \
2701 - gen_helper_##NAME##_d \
2702 - }; \
2703 - return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM); \
2825 +#define GEN_OPFV_TRANS(NAME, CHECK, FRM) \
2826 +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2827 +{ \
2828 + static gen_helper_gvec_3_ptr * const fns[3] = { \
2829 + gen_helper_##NAME##_h, \
2830 + gen_helper_##NAME##_w, \
2831 + gen_helper_##NAME##_d \
2832 + }; \
2833 + return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM, -1); \
2834 +}
2835 +
2836 +#define GEN_OPFV_BFA_TRANS(NAME, CHECK, FRM) \
2837 +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2838 +{ \
2839 + static gen_helper_gvec_3_ptr * const fns[3] = { \
2840 + gen_helper_##NAME##_h, \
2841 + gen_helper_##NAME##_w, \
2842 + gen_helper_##NAME##_d \
2843 + }; \
2844 + return do_opfv(s, a, \
2845 + (s->altfmt ? gen_helper_##NAME##_h_bf16 : \
2846 + fns[s->sew - 1]), \
2847 + CHECK, FRM, MO_16); \
2848 }
2849
2850 GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
2707 -GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN)
2708 -GEN_OPFV_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN)
2851 +GEN_OPFV_BFA_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN)
2852 +GEN_OPFV_BFA_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN)
2853
2854 /* Vector Floating-Point MIN/MAX Instructions */
2711 -GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
2712 -GEN_OPFVV_TRANS(vfmax_vv, opfvv_check)
2713 -GEN_OPFVF_TRANS(vfmin_vf, opfvf_check)
2714 -GEN_OPFVF_TRANS(vfmax_vf, opfvf_check)
2855 +GEN_OPFVV_BFA_TRANS(vfmin_vv, opfvv_check, vfmin_vv_h_bf16)
2856 +GEN_OPFVV_BFA_TRANS(vfmax_vv, opfvv_check, vfmax_vv_h_bf16)
2857 +GEN_OPFVF_BFA_TRANS(vfmin_vf, opfvf_check, vfmin_vf_h_bf16)
2858 +GEN_OPFVF_BFA_TRANS(vfmax_vf, opfvf_check, vfmax_vf_h_bf16)
2859
2860 /* Vector Floating-Point Sign-Injection Instructions */
2717 -GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check)
2718 -GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check)
2719 -GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
2720 -GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
2721 -GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
2722 -GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
2861 +GEN_OPFVV_BFA_TRANS(vfsgnj_vv, opfvv_check, vfsgnj_vv_h)
2862 +GEN_OPFVV_BFA_TRANS(vfsgnjn_vv, opfvv_check, vfsgnjn_vv_h)
2863 +GEN_OPFVV_BFA_TRANS(vfsgnjx_vv, opfvv_check, vfsgnjx_vv_h)
2864 +GEN_OPFVF_BFA_TRANS(vfsgnj_vf, opfvf_check, vfsgnj_vf_h)
2865 +GEN_OPFVF_BFA_TRANS(vfsgnjn_vf, opfvf_check, vfsgnjn_vf_h)
2866 +GEN_OPFVF_BFA_TRANS(vfsgnjx_vf, opfvf_check, vfsgnjx_vf_h)
2867
2868 /* Vector Floating-Point Compare Instructions */
2725 -static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
2869 +static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a,
2870 + int8_t valid_bfa_vsew)
2871 {
2872 return require_rvv(s) &&
2873 require_rvf(s) &&
2874 vext_check_isa_ill(s) &&
2730 - vext_check_mss(s, a->rd, a->rs1, a->rs2);
2875 + vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
2876 + vext_check_altfmt(s, valid_bfa_vsew);
2877 }
2878
2733 -GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
2734 -GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
2735 -GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
2736 -GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
2879 +GEN_OPFVV_BFA_TRANS(vmfeq_vv, opfvv_cmp_check, vmfeq_vv_h_bf16)
2880 +GEN_OPFVV_BFA_TRANS(vmfne_vv, opfvv_cmp_check, vmfne_vv_h_bf16)
2881 +GEN_OPFVV_BFA_TRANS(vmflt_vv, opfvv_cmp_check, vmflt_vv_h_bf16)
2882 +GEN_OPFVV_BFA_TRANS(vmfle_vv, opfvv_cmp_check, vmfle_vv_h_bf16)
2883
2738 -static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
2884 +static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a,
2885 + int8_t valid_bfa_vsew)
2886 {
2887 return require_rvv(s) &&
2888 require_rvf(s) &&
2889 vext_check_isa_ill(s) &&
2743 - vext_check_ms(s, a->rd, a->rs2);
2890 + vext_check_ms(s, a->rd, a->rs2) &&
2891 + vext_check_altfmt(s, valid_bfa_vsew);
2892 }
2893
2746 -GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
2747 -GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check)
2748 -GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
2749 -GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
2750 -GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
2751 -GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
2894 +GEN_OPFVF_BFA_TRANS(vmfeq_vf, opfvf_cmp_check, vmfeq_vf_h_bf16)
2895 +GEN_OPFVF_BFA_TRANS(vmfne_vf, opfvf_cmp_check, vmfne_vf_h_bf16)
2896 +GEN_OPFVF_BFA_TRANS(vmflt_vf, opfvf_cmp_check, vmflt_vf_h_bf16)
2897 +GEN_OPFVF_BFA_TRANS(vmfle_vf, opfvf_cmp_check, vmfle_vf_h_bf16)
2898 +GEN_OPFVF_BFA_TRANS(vmfgt_vf, opfvf_cmp_check, vmfgt_vf_h_bf16)
2899 +GEN_OPFVF_BFA_TRANS(vmfge_vf, opfvf_cmp_check, vmfge_vf_h_bf16)
2900
2901 /* Vector Floating-Point Classify Instruction */
2754 -GEN_OPFV_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN)
2902 +GEN_OPFV_BFA_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN)
2903
2904 /* Vector Floating-Point Merge Instruction */
2757 -GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
2905 +GEN_OPFVF_BFA_TRANS(vfmerge_vfm, opfvf_check, vfmerge_vfm_h)
2906
2907 static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
2908 {
2909 if (require_rvv(s) &&
2910 require_rvf(s) &&
2911 vext_check_isa_ill(s) &&
2764 - require_align(a->rd, s->lmul)) {
2912 + require_align(a->rd, s->lmul) &&
2913 + vext_check_altfmt(s, MO_16)) {
2914 gen_set_rm(s, RISCV_FRM_DYN);
2915
2916 TCGv_i64 t1;
@@ -2782,7 +2931,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
2931 static gen_helper_vmv_vx * const fns[3] = {
2932 gen_helper_vmv_v_x_h,
2933 gen_helper_vmv_v_x_w,
2785 - gen_helper_vmv_v_x_d,
2934 + gen_helper_vmv_v_x_d
2935 };
2936
2937 t1 = tcg_temp_new_i64();
@@ -2803,15 +2952,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
2952 }
2953
2954 /* Single-Width Floating-Point/Integer Type-Convert Instructions */
2806 -#define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \
2807 -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2808 -{ \
2809 - static gen_helper_gvec_3_ptr * const fns[3] = { \
2810 - gen_helper_##HELPER##_h, \
2811 - gen_helper_##HELPER##_w, \
2812 - gen_helper_##HELPER##_d \
2813 - }; \
2814 - return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM); \
2955 +#define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \
2956 +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2957 +{ \
2958 + static gen_helper_gvec_3_ptr * const fns[3] = { \
2959 + gen_helper_##HELPER##_h, \
2960 + gen_helper_##HELPER##_w, \
2961 + gen_helper_##HELPER##_d \
2962 + }; \
2963 + return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM, -1); \
2964 }
2965
2966 GEN_OPFV_CVT_TRANS(vfcvt_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_DYN)
@@ -2835,95 +2984,129 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
2984 vext_check_ds(s, a->rd, a->rs2, a->vm);
2985 }
2986
2838 -static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
2987 +static bool opxfv_widen_check(DisasContext *s, arg_rmr *a,
2988 + int8_t valid_bfa_vsew)
2989 {
2990 return opfv_widen_check(s, a) &&
2841 - require_rvf(s);
2991 + require_rvf(s) &&
2992 + vext_check_altfmt(s, valid_bfa_vsew);
2993 }
2994
2844 -static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
2995 +static bool opffv_widen_check(DisasContext *s, arg_rmr *a,
2996 + int8_t valid_bfa_vsew)
2997 {
2998 return opfv_widen_check(s, a) &&
2999 require_rvfmin(s) &&
2848 - require_scale_rvfmin(s);
2849 -}
2850 -
2851 -#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
2852 -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2853 -{ \
2854 - if (CHECK(s, a)) { \
2855 - uint32_t data = 0; \
2856 - static gen_helper_gvec_3_ptr * const fns[2] = { \
2857 - gen_helper_##HELPER##_h, \
2858 - gen_helper_##HELPER##_w, \
2859 - }; \
2860 - gen_set_rm_chkfrm(s, FRM); \
2861 - \
2862 - data = FIELD_DP32(data, VDATA, VM, a->vm); \
2863 - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2864 - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2865 - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2866 - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2867 - vreg_ofs(s, a->rs2), tcg_env, \
2868 - s->cfg_ptr->vlenb, \
2869 - s->cfg_ptr->vlenb, data, \
2870 - fns[s->sew - 1]); \
2871 - finalize_rvv_inst(s); \
2872 - return true; \
2873 - } \
2874 - return false; \
3000 + require_scale_rvfmin(s) &&
3001 + vext_check_altfmt(s, valid_bfa_vsew);
3002 +}
3003 +
3004 +#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
3005 +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
3006 +{ \
3007 + if (CHECK(s, a, -1)) { \
3008 + uint32_t data = 0; \
3009 + static gen_helper_gvec_3_ptr * const fns[2] = { \
3010 + gen_helper_##HELPER##_h, \
3011 + gen_helper_##HELPER##_w, \
3012 + }; \
3013 + gen_set_rm_chkfrm(s, FRM); \
3014 + \
3015 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
3016 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
3017 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
3018 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
3019 + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
3020 + vreg_ofs(s, a->rs2), tcg_env, \
3021 + s->cfg_ptr->vlenb, \
3022 + s->cfg_ptr->vlenb, data, \
3023 + fns[s->sew - 1]); \
3024 + finalize_rvv_inst(s); \
3025 + return true; \
3026 + } \
3027 + return false; \
3028 +}
3029 +
3030 +#define GEN_OPFV_WIDEN_BFA_TRANS(NAME, CHECK, HELPER, FRM, BFA_HELPER) \
3031 +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
3032 +{ \
3033 + if (CHECK(s, a, MO_16)) { \
3034 + uint32_t data = 0; \
3035 + static gen_helper_gvec_3_ptr * const fns[2] = { \
3036 + gen_helper_##HELPER##_h, \
3037 + gen_helper_##HELPER##_w, \
3038 + }; \
3039 + gen_set_rm_chkfrm(s, FRM); \
3040 + \
3041 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
3042 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
3043 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
3044 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
3045 + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
3046 + vreg_ofs(s, a->rs2), tcg_env, \
3047 + s->cfg_ptr->vlenb, \
3048 + s->cfg_ptr->vlenb, data, \
3049 + (s->altfmt ? gen_helper_##BFA_HELPER : \
3050 + fns[s->sew - 1])); \
3051 + finalize_rvv_inst(s); \
3052 + return true; \
3053 + } \
3054 + return false; \
3055 }
3056
3057 GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, opxfv_widen_check, vfwcvt_xu_f_v,
3058 RISCV_FRM_DYN)
3059 GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, opxfv_widen_check, vfwcvt_x_f_v,
3060 RISCV_FRM_DYN)
2881 -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, opffv_widen_check, vfwcvt_f_f_v,
2882 - RISCV_FRM_DYN)
3061 +GEN_OPFV_WIDEN_BFA_TRANS(vfwcvt_f_f_v, opffv_widen_check, vfwcvt_f_f_v,
3062 + RISCV_FRM_DYN, vfwcvtbf16_f_f_v)
3063 /* Reuse the helper functions from vfwcvt.xu.f.v and vfwcvt.x.f.v */
3064 GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, opxfv_widen_check, vfwcvt_xu_f_v,
3065 RISCV_FRM_RTZ)
3066 GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, opxfv_widen_check, vfwcvt_x_f_v,
3067 RISCV_FRM_RTZ)
3068
2889 -static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
3069 +static bool opfxv_widen_check(DisasContext *s, arg_rmr *a,
3070 + int8_t valid_bfa_vsew)
3071 {
3072 return require_rvv(s) &&
3073 require_scale_rvf(s) &&
3074 vext_check_isa_ill(s) &&
3075 /* OPFV widening instructions ignore vs1 check */
2895 - vext_check_ds(s, a->rd, a->rs2, a->vm);
3076 + vext_check_ds(s, a->rd, a->rs2, a->vm) &&
3077 + vext_check_altfmt(s, valid_bfa_vsew);
3078 }
3079
2898 -#define GEN_OPFXV_WIDEN_TRANS(NAME) \
2899 -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2900 -{ \
2901 - if (opfxv_widen_check(s, a)) { \
2902 - uint32_t data = 0; \
2903 - static gen_helper_gvec_3_ptr * const fns[3] = { \
2904 - gen_helper_##NAME##_b, \
2905 - gen_helper_##NAME##_h, \
2906 - gen_helper_##NAME##_w, \
2907 - }; \
2908 - gen_set_rm(s, RISCV_FRM_DYN); \
2909 - \
2910 - data = FIELD_DP32(data, VDATA, VM, a->vm); \
2911 - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2912 - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2913 - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2914 - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2915 - vreg_ofs(s, a->rs2), tcg_env, \
2916 - s->cfg_ptr->vlenb, \
2917 - s->cfg_ptr->vlenb, data, \
2918 - fns[s->sew]); \
2919 - finalize_rvv_inst(s); \
2920 - return true; \
2921 - } \
2922 - return false; \
3080 +#define GEN_OPFXV_WIDEN_BFA_TRANS(NAME) \
3081 +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
3082 +{ \
3083 + if (opfxv_widen_check(s, a, MO_8)) { \
3084 + uint32_t data = 0; \
3085 + static gen_helper_gvec_3_ptr * const fns[3] = { \
3086 + gen_helper_##NAME##_b, \
3087 + gen_helper_##NAME##_h, \
3088 + gen_helper_##NAME##_w \
3089 + }; \
3090 + gen_set_rm(s, RISCV_FRM_DYN); \
3091 + \
3092 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
3093 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
3094 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
3095 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
3096 + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
3097 + vreg_ofs(s, a->rs2), tcg_env, \
3098 + s->cfg_ptr->vlenb, \
3099 + s->cfg_ptr->vlenb, data, \
3100 + (s->altfmt ? gen_helper_##NAME##_b_bf16 : \
3101 + fns[s->sew])); \
3102 + finalize_rvv_inst(s); \
3103 + return true; \
3104 + } \
3105 + return false; \
3106 }
3107
2925 -GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v)
2926 -GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v)
3108 +GEN_OPFXV_WIDEN_BFA_TRANS(vfwcvt_f_xu_v)
3109 +GEN_OPFXV_WIDEN_BFA_TRANS(vfwcvt_f_x_v)
3110
3111 /* Narrowing Floating-Point/Integer Type-Convert Instructions */
3112
@@ -2939,104 +3122,140 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
3122 vext_check_sd(s, a->rd, a->rs2, a->vm);
3123 }
3124
2942 -static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
3125 +static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a,
3126 + int8_t valid_bfa_vsew)
3127 {
3128 return opfv_narrow_check(s, a) &&
3129 require_rvf(s) &&
2946 - (s->sew != MO_64);
3130 + (s->sew != MO_64) &&
3131 + vext_check_altfmt(s, valid_bfa_vsew);
3132 }
3133
2949 -static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
3134 +static bool opffv_narrow_check(DisasContext *s, arg_rmr *a,
3135 + int8_t valid_bfa_vsew)
3136 {
3137 return opfv_narrow_check(s, a) &&
3138 require_rvfmin(s) &&
2953 - require_scale_rvfmin(s);
3139 + require_scale_rvfmin(s) &&
3140 + vext_check_altfmt(s, valid_bfa_vsew);
3141 }
3142
2956 -static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
3143 +static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a,
3144 + int8_t valid_bfa_vsew)
3145 {
3146 return opfv_narrow_check(s, a) &&
3147 require_rvf(s) &&
2960 - require_scale_rvf(s);
2961 -}
2962 -
2963 -#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
2964 -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
2965 -{ \
2966 - if (CHECK(s, a)) { \
2967 - uint32_t data = 0; \
2968 - static gen_helper_gvec_3_ptr * const fns[2] = { \
2969 - gen_helper_##HELPER##_h, \
2970 - gen_helper_##HELPER##_w, \
2971 - }; \
2972 - gen_set_rm_chkfrm(s, FRM); \
2973 - \
2974 - data = FIELD_DP32(data, VDATA, VM, a->vm); \
2975 - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
2976 - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
2977 - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
2978 - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
2979 - vreg_ofs(s, a->rs2), tcg_env, \
2980 - s->cfg_ptr->vlenb, \
2981 - s->cfg_ptr->vlenb, data, \
2982 - fns[s->sew - 1]); \
2983 - finalize_rvv_inst(s); \
2984 - return true; \
2985 - } \
2986 - return false; \
3148 + require_scale_rvf(s) &&
3149 + vext_check_altfmt(s, valid_bfa_vsew);
3150 +}
3151 +
3152 +#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
3153 +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
3154 +{ \
3155 + if (CHECK(s, a, -1)) { \
3156 + uint32_t data = 0; \
3157 + static gen_helper_gvec_3_ptr * const fns[2] = { \
3158 + gen_helper_##HELPER##_h, \
3159 + gen_helper_##HELPER##_w, \
3160 + }; \
3161 + gen_set_rm_chkfrm(s, FRM); \
3162 + \
3163 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
3164 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
3165 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
3166 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
3167 + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
3168 + vreg_ofs(s, a->rs2), tcg_env, \
3169 + s->cfg_ptr->vlenb, \
3170 + s->cfg_ptr->vlenb, data, \
3171 + fns[s->sew - 1]); \
3172 + finalize_rvv_inst(s); \
3173 + return true; \
3174 + } \
3175 + return false; \
3176 +}
3177 +
3178 +#define GEN_OPFV_NARROW_BFA_TRANS(NAME, CHECK, HELPER, FRM, BFA_HELPER) \
3179 +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
3180 +{ \
3181 + if (CHECK(s, a, MO_16)) { \
3182 + uint32_t data = 0; \
3183 + static gen_helper_gvec_3_ptr * const fns[2] = { \
3184 + gen_helper_##HELPER##_h, \
3185 + gen_helper_##HELPER##_w, \
3186 + }; \
3187 + gen_set_rm_chkfrm(s, FRM); \
3188 + \
3189 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
3190 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
3191 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
3192 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
3193 + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
3194 + vreg_ofs(s, a->rs2), tcg_env, \
3195 + s->cfg_ptr->vlenb, \
3196 + s->cfg_ptr->vlenb, data, \
3197 + (s->altfmt ? gen_helper_##BFA_HELPER : \
3198 + fns[s->sew - 1])); \
3199 + finalize_rvv_inst(s); \
3200 + return true; \
3201 + } \
3202 + return false; \
3203 }
3204
3205 GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, opfxv_narrow_check, vfncvt_f_xu_w,
3206 RISCV_FRM_DYN)
3207 GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w,
3208 RISCV_FRM_DYN)
2993 -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
2994 - RISCV_FRM_DYN)
3209 +GEN_OPFV_NARROW_BFA_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
3210 + RISCV_FRM_DYN, vfncvtbf16_f_f_w)
3211 /* Reuse the helper function from vfncvt.f.f.w */
2996 -GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f_w,
2997 - RISCV_FRM_ROD)
3212 +GEN_OPFV_NARROW_BFA_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check,
3213 + vfncvt_f_f_w, RISCV_FRM_ROD, vfncvtbf16_f_f_w)
3214
2999 -static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
3215 +static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a,
3216 + int8_t valid_bfa_vsew)
3217 {
3218 return require_rvv(s) &&
3219 require_scale_rvf(s) &&
3220 vext_check_isa_ill(s) &&
3221 /* OPFV narrowing instructions ignore vs1 check */
3005 - vext_check_sd(s, a->rd, a->rs2, a->vm);
3222 + vext_check_sd(s, a->rd, a->rs2, a->vm) &&
3223 + vext_check_altfmt(s, valid_bfa_vsew);
3224 }
3225
3008 -#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \
3009 -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
3010 -{ \
3011 - if (opxfv_narrow_check(s, a)) { \
3012 - uint32_t data = 0; \
3013 - static gen_helper_gvec_3_ptr * const fns[3] = { \
3014 - gen_helper_##HELPER##_b, \
3015 - gen_helper_##HELPER##_h, \
3016 - gen_helper_##HELPER##_w, \
3017 - }; \
3018 - gen_set_rm_chkfrm(s, FRM); \
3019 - \
3020 - data = FIELD_DP32(data, VDATA, VM, a->vm); \
3021 - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
3022 - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
3023 - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
3024 - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
3025 - vreg_ofs(s, a->rs2), tcg_env, \
3026 - s->cfg_ptr->vlenb, \
3027 - s->cfg_ptr->vlenb, data, \
3028 - fns[s->sew]); \
3029 - finalize_rvv_inst(s); \
3030 - return true; \
3031 - } \
3032 - return false; \
3226 +#define GEN_OPXFV_NARROW_BFA_TRANS(NAME, HELPER, FRM) \
3227 +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
3228 +{ \
3229 + if (opxfv_narrow_check(s, a, MO_8)) { \
3230 + uint32_t data = 0; \
3231 + static gen_helper_gvec_3_ptr * const fns[3] = { \
3232 + gen_helper_##HELPER##_b, \
3233 + gen_helper_##HELPER##_h, \
3234 + gen_helper_##HELPER##_w \
3235 + }; \
3236 + gen_set_rm_chkfrm(s, FRM); \
3237 + \
3238 + data = FIELD_DP32(data, VDATA, VM, a->vm); \
3239 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
3240 + data = FIELD_DP32(data, VDATA, VTA, s->vta); \
3241 + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
3242 + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
3243 + vreg_ofs(s, a->rs2), tcg_env, \
3244 + s->cfg_ptr->vlenb, \
3245 + s->cfg_ptr->vlenb, data, \
3246 + (s->altfmt ? gen_helper_##HELPER##_b_bf16 : \
3247 + fns[s->sew])); \
3248 + finalize_rvv_inst(s); \
3249 + return true; \
3250 + } \
3251 + return false; \
3252 }
3253
3035 -GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN)
3036 -GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN)
3254 +GEN_OPXFV_NARROW_BFA_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN)
3255 +GEN_OPXFV_NARROW_BFA_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN)
3256 /* Reuse the helper functions from vfncvt.xu.f.w and vfncvt.x.f.w */
3038 -GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ)
3039 -GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ)
3257 +GEN_OPXFV_NARROW_BFA_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ)
3258 +GEN_OPXFV_NARROW_BFA_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ)
3259
3260 /*
3261 *** Vector Reduction Operations
@@ -3069,10 +3288,12 @@ GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
3288 GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
3289
3290 /* Vector Single-Width Floating-Point Reduction Instructions */
3072 -static bool freduction_check(DisasContext *s, arg_rmrr *a)
3291 +static bool freduction_check(DisasContext *s, arg_rmrr *a,
3292 + int8_t valid_bfa_vsew)
3293 {
3294 return reduction_check(s, a) &&
3075 - require_rvf(s);
3295 + require_rvf(s) &&
3296 + vext_check_altfmt(s, valid_bfa_vsew);
3297 }
3298
3299 GEN_OPFVV_TRANS(vfredusum_vs, freduction_check)
@@ -3081,11 +3302,13 @@ GEN_OPFVV_TRANS(vfredmax_vs, freduction_check)
3302 GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
3303
3304 /* Vector Widening Floating-Point Reduction Instructions */
3084 -static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
3305 +static bool freduction_widen_check(DisasContext *s, arg_rmrr *a,
3306 + int8_t valid_bfa_vsew)
3307 {
3308 return reduction_widen_check(s, a) &&
3309 require_rvf(s) &&
3088 - require_scale_rvf(s);
3310 + require_scale_rvf(s) &&
3311 + vext_check_altfmt(s, valid_bfa_vsew);
3312 }
3313
3314 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
@@ -3500,7 +3723,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
3723 {
3724 if (require_rvv(s) &&
3725 require_rvf(s) &&
3503 - vext_check_isa_ill(s)) {
3726 + vext_check_isa_ill(s) &&
3727 + vext_check_altfmt(s, MO_16)) {
3728 gen_set_rm(s, RISCV_FRM_DYN);
3729
3730 /* The instructions ignore LMUL and vector register group. */
@@ -3594,20 +3818,24 @@ GEN_OPIVX_VSLIDE1_TRANS(vslide1up_vx, slideup_check)
3818 GEN_OPIVX_VSLIDE1_TRANS(vslide1down_vx, slidedown_check)
3819
3820 /* Vector Floating-Point Slide Instructions */
3597 -static bool fslideup_check(DisasContext *s, arg_rmrr *a)
3821 +static bool fslideup_check(DisasContext *s, arg_rmrr *a,
3822 + int8_t valid_bfa_vsew)
3823 {
3824 return slideup_check(s, a) &&
3600 - require_rvf(s);
3825 + require_rvf(s) &&
3826 + vext_check_altfmt(s, valid_bfa_vsew);
3827 }
3828
3603 -static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
3829 +static bool fslidedown_check(DisasContext *s, arg_rmrr *a,
3830 + int8_t valid_bfa_vsew)
3831 {
3832 return slidedown_check(s, a) &&
3606 - require_rvf(s);
3833 + require_rvf(s) &&
3834 + vext_check_altfmt(s, valid_bfa_vsew);
3835 }
3836
3609 -GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
3610 -GEN_OPFVF_TRANS(vfslide1down_vf, fslidedown_check)
3837 +GEN_OPFVF_BFA_TRANS(vfslide1up_vf, fslideup_check, vfslide1up_vf_h)
3838 +GEN_OPFVF_BFA_TRANS(vfslide1down_vf, fslidedown_check, vfslide1down_vf_h)
3839
3840 /* Vector Register Gather Instruction */
3841 static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
target/riscv/internals.h
+1
@@ -84,6 +84,7 @@ FIELD(VDATA, NF, 7, 4)
84 FIELD(VDATA, WD, 7, 1)
85
86 /* float point classify helpers */
87 +target_ulong fclass_h_bf16(uint64_t frs1);
88 target_ulong fclass_h(uint64_t frs1);
89 target_ulong fclass_s(uint64_t frs1);
90 target_ulong fclass_d(uint64_t frs1);
target/riscv/vector_helper.c
+329
@@ -3168,9 +3168,11 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
3168 total_elems * ESZ); \
3169 }
3170
3171 +RVVCALL(OPFVV2, vfadd_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_add)
3172 RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
3173 RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add)
3174 RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add)
3175 +GEN_VEXT_VV_ENV(vfadd_vv_h_bf16, 2)
3176 GEN_VEXT_VV_ENV(vfadd_vv_h, 2)
3177 GEN_VEXT_VV_ENV(vfadd_vv_w, 4)
3178 GEN_VEXT_VV_ENV(vfadd_vv_d, 8)
@@ -3213,26 +3215,37 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
3215 total_elems * ESZ); \
3216 }
3217
3218 +RVVCALL(OPFVF2, vfadd_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_add)
3219 RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
3220 RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add)
3221 RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add)
3222 +GEN_VEXT_VF(vfadd_vf_h_bf16, 2)
3223 GEN_VEXT_VF(vfadd_vf_h, 2)
3224 GEN_VEXT_VF(vfadd_vf_w, 4)
3225 GEN_VEXT_VF(vfadd_vf_d, 8)
3226
3227 +RVVCALL(OPFVV2, vfsub_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_sub)
3228 RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub)
3229 RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub)
3230 RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub)
3231 +GEN_VEXT_VV_ENV(vfsub_vv_h_bf16, 2)
3232 GEN_VEXT_VV_ENV(vfsub_vv_h, 2)
3233 GEN_VEXT_VV_ENV(vfsub_vv_w, 4)
3234 GEN_VEXT_VV_ENV(vfsub_vv_d, 8)
3235 +RVVCALL(OPFVF2, vfsub_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_sub)
3236 RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub)
3237 RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub)
3238 RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub)
3239 +GEN_VEXT_VF(vfsub_vf_h_bf16, 2)
3240 GEN_VEXT_VF(vfsub_vf_h, 2)
3241 GEN_VEXT_VF(vfsub_vf_w, 4)
3242 GEN_VEXT_VF(vfsub_vf_d, 8)
3243
3244 +static uint16_t bfloat16_rsub(uint16_t a, uint16_t b, float_status * s)
3245 +{
3246 + return bfloat16_sub(b, a, s);
3247 +}
3248 +
3249 static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
3250 {
3251 return float16_sub(b, a, s);
@@ -3248,14 +3261,22 @@ static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
3261 return float64_sub(b, a, s);
3262 }
3263
3264 +RVVCALL(OPFVF2, vfrsub_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_rsub)
3265 RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub)
3266 RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub)
3267 RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
3268 +GEN_VEXT_VF(vfrsub_vf_h_bf16, 2)
3269 GEN_VEXT_VF(vfrsub_vf_h, 2)
3270 GEN_VEXT_VF(vfrsub_vf_w, 4)
3271 GEN_VEXT_VF(vfrsub_vf_d, 8)
3272
3273 /* Vector Widening Floating-Point Add/Subtract Instructions */
3274 +static uint32_t vfwadd16_bf16(uint16_t a, uint16_t b, float_status *s)
3275 +{
3276 + return float32_add(bfloat16_to_float32(a, s),
3277 + bfloat16_to_float32(b, s), s);
3278 +}
3279 +
3280 static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
3281 {
3282 return float32_add(float16_to_float32(a, true, s),
@@ -3269,15 +3290,25 @@ static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
3290
3291 }
3292
3293 +RVVCALL(OPFVV2, vfwadd_vv_h_bf16, WOP_UUU_H, H4, H2, H2, vfwadd16_bf16)
3294 RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16)
3295 RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32)
3296 +GEN_VEXT_VV_ENV(vfwadd_vv_h_bf16, 4)
3297 GEN_VEXT_VV_ENV(vfwadd_vv_h, 4)
3298 GEN_VEXT_VV_ENV(vfwadd_vv_w, 8)
3299 +RVVCALL(OPFVF2, vfwadd_vf_h_bf16, WOP_UUU_H, H4, H2, vfwadd16_bf16)
3300 RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16)
3301 RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32)
3302 +GEN_VEXT_VF(vfwadd_vf_h_bf16, 4)
3303 GEN_VEXT_VF(vfwadd_vf_h, 4)
3304 GEN_VEXT_VF(vfwadd_vf_w, 8)
3305
3306 +static uint32_t vfwsub16_bf16(uint16_t a, uint16_t b, float_status *s)
3307 +{
3308 + return float32_sub(bfloat16_to_float32(a, s),
3309 + bfloat16_to_float32(b, s), s);
3310 +}
3311 +
3312 static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
3313 {
3314 return float32_sub(float16_to_float32(a, true, s),
@@ -3291,15 +3322,24 @@ static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
3322
3323 }
3324
3325 +RVVCALL(OPFVV2, vfwsub_vv_h_bf16, WOP_UUU_H, H4, H2, H2, vfwsub16_bf16)
3326 RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16)
3327 RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32)
3328 +GEN_VEXT_VV_ENV(vfwsub_vv_h_bf16, 4)
3329 GEN_VEXT_VV_ENV(vfwsub_vv_h, 4)
3330 GEN_VEXT_VV_ENV(vfwsub_vv_w, 8)
3331 +RVVCALL(OPFVF2, vfwsub_vf_h_bf16, WOP_UUU_H, H4, H2, vfwsub16_bf16)
3332 RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16)
3333 RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32)
3334 +GEN_VEXT_VF(vfwsub_vf_h_bf16, 4)
3335 GEN_VEXT_VF(vfwsub_vf_h, 4)
3336 GEN_VEXT_VF(vfwsub_vf_w, 8)
3337
3338 +static uint32_t vfwaddw16_bf16(uint32_t a, uint16_t b, float_status *s)
3339 +{
3340 + return float32_add(a, bfloat16_to_float32(b, s), s);
3341 +}
3342 +
3343 static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s)
3344 {
3345 return float32_add(a, float16_to_float32(b, true, s), s);
@@ -3310,15 +3350,24 @@ static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s)
3350 return float64_add(a, float32_to_float64(b, s), s);
3351 }
3352
3353 +RVVCALL(OPFVV2, vfwadd_wv_h_bf16, WOP_WUUU_H, H4, H2, H2, vfwaddw16_bf16)
3354 RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16)
3355 RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32)
3356 +GEN_VEXT_VV_ENV(vfwadd_wv_h_bf16, 4)
3357 GEN_VEXT_VV_ENV(vfwadd_wv_h, 4)
3358 GEN_VEXT_VV_ENV(vfwadd_wv_w, 8)
3359 +RVVCALL(OPFVF2, vfwadd_wf_h_bf16, WOP_WUUU_H, H4, H2, vfwaddw16_bf16)
3360 RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16)
3361 RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32)
3362 +GEN_VEXT_VF(vfwadd_wf_h_bf16, 4)
3363 GEN_VEXT_VF(vfwadd_wf_h, 4)
3364 GEN_VEXT_VF(vfwadd_wf_w, 8)
3365
3366 +static uint32_t vfwsubw16_bf16(uint32_t a, uint16_t b, float_status *s)
3367 +{
3368 + return float32_sub(a, bfloat16_to_float32(b, s), s);
3369 +}
3370 +
3371 static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s)
3372 {
3373 return float32_sub(a, float16_to_float32(b, true, s), s);
@@ -3329,25 +3378,33 @@ static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s)
3378 return float64_sub(a, float32_to_float64(b, s), s);
3379 }
3380
3381 +RVVCALL(OPFVV2, vfwsub_wv_h_bf16, WOP_WUUU_H, H4, H2, H2, vfwsubw16_bf16)
3382 RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16)
3383 RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32)
3384 +GEN_VEXT_VV_ENV(vfwsub_wv_h_bf16, 4)
3385 GEN_VEXT_VV_ENV(vfwsub_wv_h, 4)
3386 GEN_VEXT_VV_ENV(vfwsub_wv_w, 8)
3387 +RVVCALL(OPFVF2, vfwsub_wf_h_bf16, WOP_WUUU_H, H4, H2, vfwsubw16_bf16)
3388 RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16)
3389 RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32)
3390 +GEN_VEXT_VF(vfwsub_wf_h_bf16, 4)
3391 GEN_VEXT_VF(vfwsub_wf_h, 4)
3392 GEN_VEXT_VF(vfwsub_wf_w, 8)
3393
3394 /* Vector Single-Width Floating-Point Multiply/Divide Instructions */
3395 +RVVCALL(OPFVV2, vfmul_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_mul)
3396 RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul)
3397 RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul)
3398 RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul)
3399 +GEN_VEXT_VV_ENV(vfmul_vv_h_bf16, 2)
3400 GEN_VEXT_VV_ENV(vfmul_vv_h, 2)
3401 GEN_VEXT_VV_ENV(vfmul_vv_w, 4)
3402 GEN_VEXT_VV_ENV(vfmul_vv_d, 8)
3403 +RVVCALL(OPFVF2, vfmul_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_mul)
3404 RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul)
3405 RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul)
3406 RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul)
3407 +GEN_VEXT_VF(vfmul_vf_h_bf16, 2)
3408 GEN_VEXT_VF(vfmul_vf_h, 2)
3409 GEN_VEXT_VF(vfmul_vf_w, 4)
3410 GEN_VEXT_VF(vfmul_vf_d, 8)
@@ -3388,6 +3445,12 @@ GEN_VEXT_VF(vfrdiv_vf_w, 4)
3445 GEN_VEXT_VF(vfrdiv_vf_d, 8)
3446
3447 /* Vector Widening Floating-Point Multiply */
3448 +static uint32_t vfwmul16_bf16(uint16_t a, uint16_t b, float_status *s)
3449 +{
3450 + return float32_mul(bfloat16_to_float32(a, s),
3451 + bfloat16_to_float32(b, s), s);
3452 +}
3453 +
3454 static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
3455 {
3456 return float32_mul(float16_to_float32(a, true, s),
@@ -3400,12 +3463,17 @@ static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
3463 float32_to_float64(b, s), s);
3464
3465 }
3466 +
3467 +RVVCALL(OPFVV2, vfwmul_vv_h_bf16, WOP_UUU_H, H4, H2, H2, vfwmul16_bf16)
3468 RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
3469 RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
3470 +GEN_VEXT_VV_ENV(vfwmul_vv_h_bf16, 4)
3471 GEN_VEXT_VV_ENV(vfwmul_vv_h, 4)
3472 GEN_VEXT_VV_ENV(vfwmul_vv_w, 8)
3473 +RVVCALL(OPFVF2, vfwmul_vf_h_bf16, WOP_UUU_H, H4, H2, vfwmul16_bf16)
3474 RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
3475 RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
3476 +GEN_VEXT_VF(vfwmul_vf_h_bf16, 4)
3477 GEN_VEXT_VF(vfwmul_vf_h, 4)
3478 GEN_VEXT_VF(vfwmul_vf_w, 8)
3479
@@ -3420,6 +3488,12 @@ static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
3488 *((TD *)vd + HD(i)) = OP(s2, s1, d, &env->fp_status); \
3489 }
3490
3491 +static uint16_t fmacc16_bf16(uint16_t a, uint16_t b, uint16_t d,
3492 + float_status *s)
3493 +{
3494 + return bfloat16_muladd(a, b, d, 0, s);
3495 +}
3496 +
3497 static uint16_t fmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
3498 {
3499 return float16_muladd(a, b, d, 0, s);
@@ -3435,9 +3509,11 @@ static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
3509 return float64_muladd(a, b, d, 0, s);
3510 }
3511
3512 +RVVCALL(OPFVV3, vfmacc_vv_h_bf16, OP_UUU_H, H2, H2, H2, fmacc16_bf16)
3513 RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
3514 RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
3515 RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
3516 +GEN_VEXT_VV_ENV(vfmacc_vv_h_bf16, 2)
3517 GEN_VEXT_VV_ENV(vfmacc_vv_h, 2)
3518 GEN_VEXT_VV_ENV(vfmacc_vv_w, 4)
3519 GEN_VEXT_VV_ENV(vfmacc_vv_d, 8)
@@ -3451,13 +3527,22 @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
3527 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d, &env->fp_status);\
3528 }
3529
3530 +RVVCALL(OPFVF3, vfmacc_vf_h_bf16, OP_UUU_H, H2, H2, fmacc16_bf16)
3531 RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16)
3532 RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32)
3533 RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64)
3534 +GEN_VEXT_VF(vfmacc_vf_h_bf16, 2)
3535 GEN_VEXT_VF(vfmacc_vf_h, 2)
3536 GEN_VEXT_VF(vfmacc_vf_w, 4)
3537 GEN_VEXT_VF(vfmacc_vf_d, 8)
3538
3539 +static uint16_t fnmacc16_bf16(uint16_t a, uint16_t b, uint16_t d,
3540 + float_status *s)
3541 +{
3542 + return bfloat16_muladd(a, b, d, float_muladd_negate_c |
3543 + float_muladd_negate_product, s);
3544 +}
3545 +
3546 static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
3547 {
3548 return float16_muladd(a, b, d, float_muladd_negate_c |
@@ -3476,19 +3561,29 @@ static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
3561 float_muladd_negate_product, s);
3562 }
3563
3564 +RVVCALL(OPFVV3, vfnmacc_vv_h_bf16, OP_UUU_H, H2, H2, H2, fnmacc16_bf16)
3565 RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
3566 RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32)
3567 RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64)
3568 +GEN_VEXT_VV_ENV(vfnmacc_vv_h_bf16, 2)
3569 GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2)
3570 GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4)
3571 GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8)
3572 +RVVCALL(OPFVF3, vfnmacc_vf_h_bf16, OP_UUU_H, H2, H2, fnmacc16_bf16)
3573 RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16)
3574 RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32)
3575 RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64)
3576 +GEN_VEXT_VF(vfnmacc_vf_h_bf16, 2)
3577 GEN_VEXT_VF(vfnmacc_vf_h, 2)
3578 GEN_VEXT_VF(vfnmacc_vf_w, 4)
3579 GEN_VEXT_VF(vfnmacc_vf_d, 8)
3580
3581 +static uint16_t fmsac16_bf16(uint16_t a, uint16_t b, uint16_t d,
3582 + float_status *s)
3583 +{
3584 + return bfloat16_muladd(a, b, d, float_muladd_negate_c, s);
3585 +}
3586 +
3587 static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
3588 {
3589 return float16_muladd(a, b, d, float_muladd_negate_c, s);
@@ -3504,19 +3599,29 @@ static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
3599 return float64_muladd(a, b, d, float_muladd_negate_c, s);
3600 }
3601
3602 +RVVCALL(OPFVV3, vfmsac_vv_h_bf16, OP_UUU_H, H2, H2, H2, fmsac16_bf16)
3603 RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16)
3604 RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32)
3605 RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64)
3606 +GEN_VEXT_VV_ENV(vfmsac_vv_h_bf16, 2)
3607 GEN_VEXT_VV_ENV(vfmsac_vv_h, 2)
3608 GEN_VEXT_VV_ENV(vfmsac_vv_w, 4)
3609 GEN_VEXT_VV_ENV(vfmsac_vv_d, 8)
3610 +RVVCALL(OPFVF3, vfmsac_vf_h_bf16, OP_UUU_H, H2, H2, fmsac16_bf16)
3611 RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16)
3612 RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32)
3613 RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64)
3614 +GEN_VEXT_VF(vfmsac_vf_h_bf16, 2)
3615 GEN_VEXT_VF(vfmsac_vf_h, 2)
3616 GEN_VEXT_VF(vfmsac_vf_w, 4)
3617 GEN_VEXT_VF(vfmsac_vf_d, 8)
3618
3619 +static uint16_t fnmsac16_bf16(uint16_t a, uint16_t b, uint16_t d,
3620 + float_status *s)
3621 +{
3622 + return bfloat16_muladd(a, b, d, float_muladd_negate_product, s);
3623 +}
3624 +
3625 static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
3626 {
3627 return float16_muladd(a, b, d, float_muladd_negate_product, s);
@@ -3532,19 +3637,29 @@ static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
3637 return float64_muladd(a, b, d, float_muladd_negate_product, s);
3638 }
3639
3640 +RVVCALL(OPFVV3, vfnmsac_vv_h_bf16, OP_UUU_H, H2, H2, H2, fnmsac16_bf16)
3641 RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16)
3642 RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32)
3643 RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64)
3644 +GEN_VEXT_VV_ENV(vfnmsac_vv_h_bf16, 2)
3645 GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2)
3646 GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4)
3647 GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8)
3648 +RVVCALL(OPFVF3, vfnmsac_vf_h_bf16, OP_UUU_H, H2, H2, fnmsac16_bf16)
3649 RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16)
3650 RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32)
3651 RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64)
3652 +GEN_VEXT_VF(vfnmsac_vf_h_bf16, 2)
3653 GEN_VEXT_VF(vfnmsac_vf_h, 2)
3654 GEN_VEXT_VF(vfnmsac_vf_w, 4)
3655 GEN_VEXT_VF(vfnmsac_vf_d, 8)
3656
3657 +static uint16_t fmadd16_bf16(uint16_t a, uint16_t b, uint16_t d,
3658 + float_status *s)
3659 +{
3660 + return bfloat16_muladd(d, b, a, 0, s);
3661 +}
3662 +
3663 static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
3664 {
3665 return float16_muladd(d, b, a, 0, s);
@@ -3560,19 +3675,30 @@ static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
3675 return float64_muladd(d, b, a, 0, s);
3676 }
3677
3678 +RVVCALL(OPFVV3, vfmadd_vv_h_bf16, OP_UUU_H, H2, H2, H2, fmadd16_bf16)
3679 RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16)
3680 RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32)
3681 RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64)
3682 +GEN_VEXT_VV_ENV(vfmadd_vv_h_bf16, 2)
3683 GEN_VEXT_VV_ENV(vfmadd_vv_h, 2)
3684 GEN_VEXT_VV_ENV(vfmadd_vv_w, 4)
3685 GEN_VEXT_VV_ENV(vfmadd_vv_d, 8)
3686 +RVVCALL(OPFVF3, vfmadd_vf_h_bf16, OP_UUU_H, H2, H2, fmadd16_bf16)
3687 RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16)
3688 RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32)
3689 RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64)
3690 +GEN_VEXT_VF(vfmadd_vf_h_bf16, 2)
3691 GEN_VEXT_VF(vfmadd_vf_h, 2)
3692 GEN_VEXT_VF(vfmadd_vf_w, 4)
3693 GEN_VEXT_VF(vfmadd_vf_d, 8)
3694
3695 +static uint16_t fnmadd16_bf16(uint16_t a, uint16_t b, uint16_t d,
3696 + float_status *s)
3697 +{
3698 + return bfloat16_muladd(d, b, a, float_muladd_negate_c |
3699 + float_muladd_negate_product, s);
3700 +}
3701 +
3702 static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
3703 {
3704 return float16_muladd(d, b, a, float_muladd_negate_c |
@@ -3591,19 +3717,29 @@ static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
3717 float_muladd_negate_product, s);
3718 }
3719
3720 +RVVCALL(OPFVV3, vfnmadd_vv_h_bf16, OP_UUU_H, H2, H2, H2, fnmadd16_bf16)
3721 RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
3722 RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32)
3723 RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64)
3724 +GEN_VEXT_VV_ENV(vfnmadd_vv_h_bf16, 2)
3725 GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2)
3726 GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4)
3727 GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8)
3728 +RVVCALL(OPFVF3, vfnmadd_vf_h_bf16, OP_UUU_H, H2, H2, fnmadd16_bf16)
3729 RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16)
3730 RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32)
3731 RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64)
3732 +GEN_VEXT_VF(vfnmadd_vf_h_bf16, 2)
3733 GEN_VEXT_VF(vfnmadd_vf_h, 2)
3734 GEN_VEXT_VF(vfnmadd_vf_w, 4)
3735 GEN_VEXT_VF(vfnmadd_vf_d, 8)
3736
3737 +static uint16_t fmsub16_bf16(uint16_t a, uint16_t b, uint16_t d,
3738 + float_status *s)
3739 +{
3740 + return bfloat16_muladd(d, b, a, float_muladd_negate_c, s);
3741 +}
3742 +
3743 static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
3744 {
3745 return float16_muladd(d, b, a, float_muladd_negate_c, s);
@@ -3619,19 +3755,29 @@ static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
3755 return float64_muladd(d, b, a, float_muladd_negate_c, s);
3756 }
3757
3758 +RVVCALL(OPFVV3, vfmsub_vv_h_bf16, OP_UUU_H, H2, H2, H2, fmsub16_bf16)
3759 RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16)
3760 RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32)
3761 RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64)
3762 +GEN_VEXT_VV_ENV(vfmsub_vv_h_bf16, 2)
3763 GEN_VEXT_VV_ENV(vfmsub_vv_h, 2)
3764 GEN_VEXT_VV_ENV(vfmsub_vv_w, 4)
3765 GEN_VEXT_VV_ENV(vfmsub_vv_d, 8)
3766 +RVVCALL(OPFVF3, vfmsub_vf_h_bf16, OP_UUU_H, H2, H2, fmsub16_bf16)
3767 RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16)
3768 RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32)
3769 RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64)
3770 +GEN_VEXT_VF(vfmsub_vf_h_bf16, 2)
3771 GEN_VEXT_VF(vfmsub_vf_h, 2)
3772 GEN_VEXT_VF(vfmsub_vf_w, 4)
3773 GEN_VEXT_VF(vfmsub_vf_d, 8)
3774
3775 +static uint16_t fnmsub16_bf16(uint16_t a, uint16_t b, uint16_t d,
3776 + float_status *s)
3777 +{
3778 + return bfloat16_muladd(d, b, a, float_muladd_negate_product, s);
3779 +}
3780 +
3781 static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
3782 {
3783 return float16_muladd(d, b, a, float_muladd_negate_product, s);
@@ -3647,15 +3793,19 @@ static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
3793 return float64_muladd(d, b, a, float_muladd_negate_product, s);
3794 }
3795
3796 +RVVCALL(OPFVV3, vfnmsub_vv_h_bf16, OP_UUU_H, H2, H2, H2, fnmsub16_bf16)
3797 RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16)
3798 RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32)
3799 RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64)
3800 +GEN_VEXT_VV_ENV(vfnmsub_vv_h_bf16, 2)
3801 GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2)
3802 GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4)
3803 GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8)
3804 +RVVCALL(OPFVF3, vfnmsub_vf_h_bf16, OP_UUU_H, H2, H2, fnmsub16_bf16)
3805 RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16)
3806 RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32)
3807 RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
3808 +GEN_VEXT_VF(vfnmsub_vf_h_bf16, 2)
3809 GEN_VEXT_VF(vfnmsub_vf_h, 2)
3810 GEN_VEXT_VF(vfnmsub_vf_w, 4)
3811 GEN_VEXT_VF(vfnmsub_vf_d, 8)
@@ -3693,6 +3843,15 @@ GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4)
3843 RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmaccbf16)
3844 GEN_VEXT_VF(vfwmaccbf16_vf, 4)
3845
3846 +static uint32_t fwnmacc16_bf16(uint16_t a, uint16_t b, uint32_t d,
3847 + float_status *s)
3848 +{
3849 + return float32_muladd(bfloat16_to_float32(a, s),
3850 + bfloat16_to_float32(b, s), d,
3851 + float_muladd_negate_c | float_muladd_negate_product,
3852 + s);
3853 +}
3854 +
3855 static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
3856 {
3857 return float32_muladd(float16_to_float32(a, true, s),
@@ -3708,15 +3867,27 @@ static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
3867 float_muladd_negate_product, s);
3868 }
3869
3870 +RVVCALL(OPFVV3, vfwnmacc_vv_h_bf16, WOP_UUU_H, H4, H2, H2, fwnmacc16_bf16)
3871 RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
3872 RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32)
3873 +GEN_VEXT_VV_ENV(vfwnmacc_vv_h_bf16, 4)
3874 GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 4)
3875 GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 8)
3876 +RVVCALL(OPFVF3, vfwnmacc_vf_h_bf16, WOP_UUU_H, H4, H2, fwnmacc16_bf16)
3877 RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16)
3878 RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32)
3879 +GEN_VEXT_VF(vfwnmacc_vf_h_bf16, 4)
3880 GEN_VEXT_VF(vfwnmacc_vf_h, 4)
3881 GEN_VEXT_VF(vfwnmacc_vf_w, 8)
3882
3883 +static uint32_t fwmsac16_bf16(uint16_t a, uint16_t b, uint32_t d,
3884 + float_status *s)
3885 +{
3886 + return float32_muladd(bfloat16_to_float32(a, s),
3887 + bfloat16_to_float32(b, s), d,
3888 + float_muladd_negate_c, s);
3889 +}
3890 +
3891 static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
3892 {
3893 return float32_muladd(float16_to_float32(a, true, s),
@@ -3731,15 +3902,27 @@ static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
3902 float_muladd_negate_c, s);
3903 }
3904
3905 +RVVCALL(OPFVV3, vfwmsac_vv_h_bf16, WOP_UUU_H, H4, H2, H2, fwmsac16_bf16)
3906 RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
3907 RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32)
3908 +GEN_VEXT_VV_ENV(vfwmsac_vv_h_bf16, 4)
3909 GEN_VEXT_VV_ENV(vfwmsac_vv_h, 4)
3910 GEN_VEXT_VV_ENV(vfwmsac_vv_w, 8)
3911 +RVVCALL(OPFVF3, vfwmsac_vf_h_bf16, WOP_UUU_H, H4, H2, fwmsac16_bf16)
3912 RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16)
3913 RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32)
3914 +GEN_VEXT_VF(vfwmsac_vf_h_bf16, 4)
3915 GEN_VEXT_VF(vfwmsac_vf_h, 4)
3916 GEN_VEXT_VF(vfwmsac_vf_w, 8)
3917
3918 +static uint32_t fwnmsac16_bf16(uint16_t a, uint16_t b, uint32_t d,
3919 + float_status *s)
3920 +{
3921 + return float32_muladd(bfloat16_to_float32(a, s),
3922 + bfloat16_to_float32(b, s), d,
3923 + float_muladd_negate_product, s);
3924 +}
3925 +
3926 static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
3927 {
3928 return float32_muladd(float16_to_float32(a, true, s),
@@ -3754,12 +3937,16 @@ static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
3937 float_muladd_negate_product, s);
3938 }
3939
3940 +RVVCALL(OPFVV3, vfwnmsac_vv_h_bf16, WOP_UUU_H, H4, H2, H2, fwnmsac16_bf16)
3941 RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
3942 RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32)
3943 +GEN_VEXT_VV_ENV(vfwnmsac_vv_h_bf16, 4)
3944 GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 4)
3945 GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 8)
3946 +RVVCALL(OPFVF3, vfwnmsac_vf_h_bf16, WOP_UUU_H, H4, H2, fwnmsac16_bf16)
3947 RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16)
3948 RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32)
3949 +GEN_VEXT_VF(vfwnmsac_vf_h_bf16, 4)
3950 GEN_VEXT_VF(vfwnmsac_vf_h, 4)
3951 GEN_VEXT_VF(vfwnmsac_vf_w, 8)
3952
@@ -3865,6 +4052,46 @@ static uint64_t frsqrt7(uint64_t f, int exp_size, int frac_size)
4052 return val;
4053 }
4054
4055 +static bfloat16 frsqrt7_h_bf16(bfloat16 f, float_status *s)
4056 +{
4057 + int exp_size = 8, frac_size = 7;
4058 + bool sign = bfloat16_is_neg(f);
4059 +
4060 + /*
4061 + * frsqrt7(sNaN) = canonical NaN
4062 + * frsqrt7(-inf) = canonical NaN
4063 + * frsqrt7(-normal) = canonical NaN
4064 + * frsqrt7(-subnormal) = canonical NaN
4065 + */
4066 + if (bfloat16_is_signaling_nan(f, s) ||
4067 + (bfloat16_is_infinity(f) && sign) ||
4068 + (bfloat16_is_normal(f) && sign) ||
4069 + (bfloat16_is_zero_or_denormal(f) && !bfloat16_is_zero(f) && sign)) {
4070 + s->float_exception_flags |= float_flag_invalid;
4071 + return bfloat16_default_nan(s);
4072 + }
4073 +
4074 + /* frsqrt7(qNaN) = canonical NaN */
4075 + if (bfloat16_is_quiet_nan(f, s)) {
4076 + return bfloat16_default_nan(s);
4077 + }
4078 +
4079 + /* frsqrt7(+-0) = +-inf */
4080 + if (bfloat16_is_zero(f)) {
4081 + s->float_exception_flags |= float_flag_divbyzero;
4082 + return bfloat16_set_sign(bfloat16_infinity, sign);
4083 + }
4084 +
4085 + /* frsqrt7(+inf) = +0 */
4086 + if (bfloat16_is_infinity(f) && !sign) {
4087 + return bfloat16_set_sign(bfloat16_zero, sign);
4088 + }
4089 +
4090 + /* +normal, +subnormal */
4091 + uint64_t val = frsqrt7(f, exp_size, frac_size);
4092 + return make_float16(val);
4093 +}
4094 +
4095 static float16 frsqrt7_h(float16 f, float_status *s)
4096 {
4097 int exp_size = 5, frac_size = 10;
@@ -3985,9 +4212,11 @@ static float64 frsqrt7_d(float64 f, float_status *s)
4212 return make_float64(val);
4213 }
4214
4215 +RVVCALL(OPFVV1, vfrsqrt7_v_h_bf16, OP_UU_H, H2, H2, frsqrt7_h_bf16)
4216 RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h)
4217 RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s)
4218 RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d)
4219 +GEN_VEXT_V_ENV(vfrsqrt7_v_h_bf16, 2)
4220 GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2)
4221 GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4)
4222 GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8)
@@ -4080,6 +4309,38 @@ static uint64_t frec7(uint64_t f, int exp_size, int frac_size,
4309 return val;
4310 }
4311
4312 +static bfloat16 frec7_h_bf16(bfloat16 f, float_status *s)
4313 +{
4314 + int exp_size = 8, frac_size = 7;
4315 + bool sign = bfloat16_is_neg(f);
4316 +
4317 + /* frec7(+-inf) = +-0 */
4318 + if (bfloat16_is_infinity(f)) {
4319 + return bfloat16_set_sign(bfloat16_zero, sign);
4320 + }
4321 +
4322 + /* frec7(+-0) = +-inf */
4323 + if (bfloat16_is_zero(f)) {
4324 + s->float_exception_flags |= float_flag_divbyzero;
4325 + return bfloat16_set_sign(bfloat16_infinity, sign);
4326 + }
4327 +
4328 + /* frec7(sNaN) = canonical NaN */
4329 + if (bfloat16_is_signaling_nan(f, s)) {
4330 + s->float_exception_flags |= float_flag_invalid;
4331 + return bfloat16_default_nan(s);
4332 + }
4333 +
4334 + /* frec7(qNaN) = canonical NaN */
4335 + if (bfloat16_is_quiet_nan(f, s)) {
4336 + return bfloat16_default_nan(s);
4337 + }
4338 +
4339 + /* +-normal, +-subnormal */
4340 + uint64_t val = frec7(f, exp_size, frac_size, s);
4341 + return make_float16(val);
4342 +}
4343 +
4344 static float16 frec7_h(float16 f, float_status *s)
4345 {
4346 int exp_size = 5, frac_size = 10;
@@ -4176,36 +4437,46 @@ static float64 frec7_d(float64 f, float_status *s)
4437 return make_float64(val);
4438 }
4439
4440 +RVVCALL(OPFVV1, vfrec7_v_h_bf16, OP_UU_H, H2, H2, frec7_h_bf16)
4441 RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h)
4442 RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s)
4443 RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d)
4444 +GEN_VEXT_V_ENV(vfrec7_v_h_bf16, 2)
4445 GEN_VEXT_V_ENV(vfrec7_v_h, 2)
4446 GEN_VEXT_V_ENV(vfrec7_v_w, 4)
4447 GEN_VEXT_V_ENV(vfrec7_v_d, 8)
4448
4449 /* Vector Floating-Point MIN/MAX Instructions */
4450 +RVVCALL(OPFVV2, vfmin_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_minimum_number)
4451 RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number)
4452 RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number)
4453 RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number)
4454 +GEN_VEXT_VV_ENV(vfmin_vv_h_bf16, 2)
4455 GEN_VEXT_VV_ENV(vfmin_vv_h, 2)
4456 GEN_VEXT_VV_ENV(vfmin_vv_w, 4)
4457 GEN_VEXT_VV_ENV(vfmin_vv_d, 8)
4458 +RVVCALL(OPFVF2, vfmin_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_minimum_number)
4459 RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number)
4460 RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number)
4461 RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number)
4462 +GEN_VEXT_VF(vfmin_vf_h_bf16, 2)
4463 GEN_VEXT_VF(vfmin_vf_h, 2)
4464 GEN_VEXT_VF(vfmin_vf_w, 4)
4465 GEN_VEXT_VF(vfmin_vf_d, 8)
4466
4467 +RVVCALL(OPFVV2, vfmax_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_maximum_number)
4468 RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number)
4469 RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number)
4470 RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number)
4471 +GEN_VEXT_VV_ENV(vfmax_vv_h_bf16, 2)
4472 GEN_VEXT_VV_ENV(vfmax_vv_h, 2)
4473 GEN_VEXT_VV_ENV(vfmax_vv_w, 4)
4474 GEN_VEXT_VV_ENV(vfmax_vv_d, 8)
4475 +RVVCALL(OPFVF2, vfmax_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_maximum_number)
4476 RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number)
4477 RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number)
4478 RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number)
4479 +GEN_VEXT_VF(vfmax_vf_h_bf16, 2)
4480 GEN_VEXT_VF(vfmax_vf_h, 2)
4481 GEN_VEXT_VF(vfmax_vf_w, 4)
4482 GEN_VEXT_VF(vfmax_vf_d, 8)
@@ -4334,6 +4605,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
4605 } \
4606 }
4607
4608 +GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h_bf16, uint16_t, H2, bfloat16_eq_quiet)
4609 GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet)
4610 GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet)
4611 GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet)
@@ -4375,10 +4647,17 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
4647 } \
4648 }
4649
4650 +GEN_VEXT_CMP_VF(vmfeq_vf_h_bf16, uint16_t, H2, bfloat16_eq_quiet)
4651 GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet)
4652 GEN_VEXT_CMP_VF(vmfeq_vf_w, uint32_t, H4, float32_eq_quiet)
4653 GEN_VEXT_CMP_VF(vmfeq_vf_d, uint64_t, H8, float64_eq_quiet)
4654
4655 +static bool vmfne16_bf16(uint16_t a, uint16_t b, float_status *s)
4656 +{
4657 + FloatRelation compare = bfloat16_compare_quiet(a, b, s);
4658 + return compare != float_relation_equal;
4659 +}
4660 +
4661 static bool vmfne16(uint16_t a, uint16_t b, float_status *s)
4662 {
4663 FloatRelation compare = float16_compare_quiet(a, b, s);
@@ -4397,27 +4676,39 @@ static bool vmfne64(uint64_t a, uint64_t b, float_status *s)
4676 return compare != float_relation_equal;
4677 }
4678
4679 +GEN_VEXT_CMP_VV_ENV(vmfne_vv_h_bf16, uint16_t, H2, vmfne16_bf16)
4680 GEN_VEXT_CMP_VV_ENV(vmfne_vv_h, uint16_t, H2, vmfne16)
4681 GEN_VEXT_CMP_VV_ENV(vmfne_vv_w, uint32_t, H4, vmfne32)
4682 GEN_VEXT_CMP_VV_ENV(vmfne_vv_d, uint64_t, H8, vmfne64)
4683 +GEN_VEXT_CMP_VF(vmfne_vf_h_bf16, uint16_t, H2, vmfne16_bf16)
4684 GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16)
4685 GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32)
4686 GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64)
4687
4688 +GEN_VEXT_CMP_VV_ENV(vmflt_vv_h_bf16, uint16_t, H2, bfloat16_lt)
4689 GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt)
4690 GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt)
4691 GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt)
4692 +GEN_VEXT_CMP_VF(vmflt_vf_h_bf16, uint16_t, H2, bfloat16_lt)
4693 GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt)
4694 GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt)
4695 GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt)
4696
4697 +GEN_VEXT_CMP_VV_ENV(vmfle_vv_h_bf16, uint16_t, H2, bfloat16_le)
4698 GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le)
4699 GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le)
4700 GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le)
4701 +GEN_VEXT_CMP_VF(vmfle_vf_h_bf16, uint16_t, H2, bfloat16_le)
4702 GEN_VEXT_CMP_VF(vmfle_vf_h, uint16_t, H2, float16_le)
4703 GEN_VEXT_CMP_VF(vmfle_vf_w, uint32_t, H4, float32_le)
4704 GEN_VEXT_CMP_VF(vmfle_vf_d, uint64_t, H8, float64_le)
4705
4706 +static bool vmfgt16_bf16(uint16_t a, uint16_t b, float_status *s)
4707 +{
4708 + FloatRelation compare = bfloat16_compare(a, b, s);
4709 + return compare == float_relation_greater;
4710 +}
4711 +
4712 static bool vmfgt16(uint16_t a, uint16_t b, float_status *s)
4713 {
4714 FloatRelation compare = float16_compare(a, b, s);
@@ -4436,10 +4727,18 @@ static bool vmfgt64(uint64_t a, uint64_t b, float_status *s)
4727 return compare == float_relation_greater;
4728 }
4729
4730 +GEN_VEXT_CMP_VF(vmfgt_vf_h_bf16, uint16_t, H2, vmfgt16_bf16)
4731 GEN_VEXT_CMP_VF(vmfgt_vf_h, uint16_t, H2, vmfgt16)
4732 GEN_VEXT_CMP_VF(vmfgt_vf_w, uint32_t, H4, vmfgt32)
4733 GEN_VEXT_CMP_VF(vmfgt_vf_d, uint64_t, H8, vmfgt64)
4734
4735 +static bool vmfge16_bf16(uint16_t a, uint16_t b, float_status *s)
4736 +{
4737 + FloatRelation compare = bfloat16_compare(a, b, s);
4738 + return compare == float_relation_greater ||
4739 + compare == float_relation_equal;
4740 +}
4741 +
4742 static bool vmfge16(uint16_t a, uint16_t b, float_status *s)
4743 {
4744 FloatRelation compare = float16_compare(a, b, s);
@@ -4461,11 +4760,31 @@ static bool vmfge64(uint64_t a, uint64_t b, float_status *s)
4760 compare == float_relation_equal;
4761 }
4762
4763 +GEN_VEXT_CMP_VF(vmfge_vf_h_bf16, uint16_t, H2, vmfge16_bf16)
4764 GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16)
4765 GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
4766 GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
4767
4768 /* Vector Floating-Point Classify Instruction */
4769 +target_ulong fclass_h_bf16(uint64_t frs1)
4770 +{
4771 + bfloat16 f = frs1;
4772 + bool sign = bfloat16_is_neg(f);
4773 +
4774 + if (bfloat16_is_infinity(f)) {
4775 + return sign ? 1 << 0 : 1 << 7;
4776 + } else if (bfloat16_is_zero(f)) {
4777 + return sign ? 1 << 3 : 1 << 4;
4778 + } else if (bfloat16_is_zero_or_denormal(f)) {
4779 + return sign ? 1 << 2 : 1 << 5;
4780 + } else if (bfloat16_is_any_nan(f)) {
4781 + float_status s = { }; /* for snan_bit_is_one */
4782 + return bfloat16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
4783 + } else {
4784 + return sign ? 1 << 1 : 1 << 6;
4785 + }
4786 +}
4787 +
4788 target_ulong fclass_h(uint64_t frs1)
4789 {
4790 float16 f = frs1;
@@ -4523,9 +4842,11 @@ target_ulong fclass_d(uint64_t frs1)
4842 }
4843 }
4844
4845 +RVVCALL(OPIVV1, vfclass_v_h_bf16, OP_UU_H, H2, H2, fclass_h_bf16)
4846 RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h)
4847 RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s)
4848 RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
4849 +GEN_VEXT_V(vfclass_v_h_bf16, 2)
4850 GEN_VEXT_V(vfclass_v_h, 2)
4851 GEN_VEXT_V(vfclass_v_w, 4)
4852 GEN_VEXT_V(vfclass_v_d, 8)
@@ -4616,17 +4937,21 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 8)
4937 * vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float.
4938 */
4939 RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
4940 +RVVCALL(OPFVV1, vfwcvt_f_xu_v_b_bf16, WOP_UU_B, H2, H1, uint8_to_bfloat16)
4941 RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
4942 RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
4943 GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 2)
4944 +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b_bf16, 2)
4945 GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 4)
4946 GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 8)
4947
4948 /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
4949 RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
4950 +RVVCALL(OPFVV1, vfwcvt_f_x_v_b_bf16, WOP_UU_B, H2, H1, int8_to_bfloat16)
4951 RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
4952 RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
4953 GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 2)
4954 +GEN_VEXT_V_ENV(vfwcvt_f_x_v_b_bf16, 2)
4955 GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 4)
4956 GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 8)
4957
@@ -4653,17 +4978,21 @@ GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v, 4)
4978 #define NOP_UU_W uint32_t, uint64_t, uint64_t
4979 /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
4980 RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
4981 +RVVCALL(OPFVV1, vfncvt_xu_f_w_b_bf16, NOP_UU_B, H1, H2, bfloat16_to_uint8)
4982 RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
4983 RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
4984 GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1)
4985 +GEN_VEXT_V_ENV(vfncvt_xu_f_w_b_bf16, 1)
4986 GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2)
4987 GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4)
4988
4989 /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
4990 RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
4991 +RVVCALL(OPFVV1, vfncvt_x_f_w_b_bf16, NOP_UU_B, H1, H2, bfloat16_to_int8)
4992 RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
4993 RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
4994 GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1)
4995 +GEN_VEXT_V_ENV(vfncvt_x_f_w_b_bf16, 1)
4996 GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2)
4997 GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4)
4998