@samitouri / QOSamiQemu / commits / ee0f1ce00d

target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns

In the GICv5 architecture, part of the GIC is implemented inside the CPU: this is the CPU interface, which presents software with system instructions and system registers, and communicates with the external part of the GIC (the Interrupt Routing Service, IRS) via an architected stream interface where both sides can send commands and receive responses. Add the initial source files for the GICv5 CPU interface, with initial content implementing just the two GSB GIC barrier instructions, which are no-ops for QEMU. Since we will not initially implement virtualization or the "legacy GICv3" interface that can be provided to a VM guest, we don't have the ICH_VCTLR_EL2 register and do not need to implement an accessfn for the "trap if at EL1 and EL2 enabled and legacy GICv3 is enabled" handling. We will come back and add this later as part of the legacy-GICv3 code. (The GICv3 has a similar architecture with part of the GIC being in the CPU and part external; for QEMU we implemented the CPU interface in hw/intc/, but in retrospect I think this was something of a design mistake, and for GICv5 I am going to stick a bit closer to how the hardware architecture splits things up; hence this code is in target/arm.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-15-peter.maydell@linaro.org

Peter Maydell committed Mar 27, 2026 at 11:16 UTC ee0f1ce00dbbef5b520b75f442a4a6c85b7f5d2f
5 files changed +54
target/arm/cpu-features.h
+6
@@ -280,6 +280,7 @@ FIELD(ID_AA64PFR1, PFAR, 60, 4)
280 FIELD(ID_AA64PFR2, MTEPERM, 0, 4)
281 FIELD(ID_AA64PFR2, MTESTOREONLY, 4, 4)
282 FIELD(ID_AA64PFR2, MTEFAR, 8, 4)
283 +FIELD(ID_AA64PFR2, GCIE, 12, 4)
284 FIELD(ID_AA64PFR2, FPMR, 32, 4)
285
286 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
@@ -1172,6 +1173,11 @@ static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id)
1173 return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) != 0;
1174 }
1175
1176 +static inline bool isar_feature_aa64_gcie(const ARMISARegisters *id)
1177 +{
1178 + return FIELD_EX64_IDREG(id, ID_AA64PFR2, GCIE) != 0;
1179 +}
1180 +
1181 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
1182 {
1183 return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1;
target/arm/helper.c
+1
@@ -6233,6 +6233,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
6233 if (tcg_enabled()) {
6234 define_tlb_insn_regs(cpu);
6235 define_at_insn_regs(cpu);
6236 + define_gicv5_cpuif_regs(cpu);
6237 }
6238 #endif
6239
target/arm/internals.h
+3
@@ -1810,6 +1810,9 @@ void define_gcs_cpregs(ARMCPU *cpu);
1810 /* Add the cpreg definitions for OMAP CP15 regs */
1811 void define_omap_cp_regs(ARMCPU *cpu);
1812
1813 +/* Add the cpreg definitions for the GICv5 CPU interface */
1814 +void define_gicv5_cpuif_regs(ARMCPU *cpu);
1815 +
1816 /* Effective value of MDCR_EL2 */
1817 static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
1818 {
target/arm/tcg/gicv5-cpuif.c new
+43
@@ -0,0 +1,43 @@
1 +/*
2 + * GICv5 CPU interface
3 + *
4 + * Copyright (c) 2025 Linaro Limited
5 + *
6 + * SPDX-License-Identifier: GPL-2.0-or-later
7 + */
8 +
9 +#include "qemu/osdep.h"
10 +#include "cpu.h"
11 +#include "internals.h"
12 +#include "cpregs.h"
13 +
14 +static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
15 + /*
16 + * Barrier: wait until the effects of a cpuif system register
17 + * write have definitely made it to the IRS (and will thus show up
18 + * in cpuif reads from the IRS by this or other CPUs and in the
19 + * status of IRQ, FIQ etc). For QEMU we do all interaction with
20 + * the IRS synchronously, so we can make this a nop.
21 + */
22 + { .name = "GSB_SYS", .state = ARM_CP_STATE_AA64,
23 + .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 0,
24 + .access = PL1_W, .type = ARM_CP_NOP,
25 + },
26 + /*
27 + * Barrier: wait until the effects of acknowledging an interrupt
28 + * (via GICR CDIA or GICR CDNMIA) are visible, including the
29 + * effect on the {IRQ,FIQ,vIRQ,vFIQ} pending state. This is a
30 + * weaker version of GSB SYS. Again, for QEMU this is a nop.
31 + */
32 + { .name = "GSB_ACK", .state = ARM_CP_STATE_AA64,
33 + .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
34 + .access = PL1_W, .type = ARM_CP_NOP,
35 + },
36 +};
37 +
38 +void define_gicv5_cpuif_regs(ARMCPU *cpu)
39 +{
40 + if (cpu_isar_feature(aa64_gcie, cpu)) {
41 + define_arm_cp_regs(cpu, gicv5_cpuif_reginfo);
42 + }
43 +}
target/arm/tcg/meson.build
+1
@@ -67,6 +67,7 @@ arm_common_system_ss.add(
67 files(
68 'cpregs-at.c',
69 'debug.c',
70 + 'gicv5-cpuif.c',
71 'hflags.c',
72 'gengvec.c',
73 'm_helper.c',