target/arm: GICv5 cpuif: Implement PPI priority registers
Implement the GICv5 registers which hold the priority of the PPIs. Each 64-bit register has the priority fields for 8 PPIs, so there are 16 registers in total. This would be a lot of duplication if we wrote it out statically in the array, so instead create each register via a loop in define_gicv5_cpuif_regs(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-41-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
ef540c1d301d5129fdccb5ad414131c9c090a362
2 files changed
+25
target/arm/cpu.h
+2
@@ -607,6 +607,8 @@ typedef struct CPUArchState {
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uint64_t ppi_hm[GICV5_NUM_PPIS / 64];
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uint64_t ppi_pend[GICV5_NUM_PPIS / 64];
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uint64_t ppi_enable[GICV5_NUM_PPIS / 64];
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+ /* The PRIO regs have 1 byte per PPI, so 8 PPIs to a register */
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+ uint64_t ppi_priority[GICV5_NUM_PPIS / 8];
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} gicv5_cpuif;
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struct {
target/arm/tcg/gicv5-cpuif.c
+23
@@ -225,6 +225,12 @@ static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri,
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raw_write(env, ri, value);
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}
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+static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri,
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+ uint64_t value)
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+{
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+ raw_write(env, ri, value);
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+}
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+
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static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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/*
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* Barrier: wait until the effects of a cpuif system register
@@ -382,5 +388,22 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu)
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{
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if (cpu_isar_feature(aa64_gcie, cpu)) {
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define_arm_cp_regs(cpu, gicv5_cpuif_reginfo);
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+
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+ /*
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+ * There are 16 ICC_PPI_PRIORITYR<n>_EL1 regs, so define them
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+ * programmatically rather than listing them all statically.
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+ */
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+ for (int i = 0; i < 16; i++) {
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+ g_autofree char *name = g_strdup_printf("ICC_PPI_PRIORITYR%d_EL1", i);
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+ ARMCPRegInfo ppi_prio = {
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+ .name = name, .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 0, .crn = 12,
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+ .crm = 14 + (i >> 3), .opc2 = i & 7,
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+ .access = PL1_RW, .type = ARM_CP_IO,
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+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_priority[i]),
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+ .writefn = gic_ppi_priority_write, .raw_writefn = raw_write,
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+ };
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+ define_one_arm_cp_reg(cpu, &ppi_prio);
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+ }
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}
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}