target/riscv: Update MISA.C for Zc* extensions
MISA.C is set if the following extensions are selected: * Zca and not F. * Zca, Zcf and F (but not D) is specified (RV32 only). * Zca, Zcf and Zcd if D is specified (RV32 only). * Zca, Zcd if D is specified (RV64 only). Therefore, MISA.C must be set according to the Zc* extension rules. Warn the user if RVC is explicitly disabled but MISA.C is required by the rules above. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Max Chou <max.chou@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260424050509.3935180-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang committed
Apr 24, 2026 at 13:05 UTC
f0433a8bc4ac5626499ff09ba5d165dbf7a4a980
1 file changed
+39
target/riscv/tcg/tcg-cpu.c
+39
@@ -1163,6 +1163,44 @@ static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
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}
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}
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+/*
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+ * MISA.C is set if the following extensions are selected:
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+ * - Zca and not F.
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+ * - Zca, Zcf and F (but not D) is specified on RV32.
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+ * - Zca, Zcf and Zcd if D is specified on RV32.
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+ * - Zca, Zcd if D is specified on RV64.
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+ */
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+static void riscv_cpu_update_misa_c(RISCVCPU *cpu)
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+{
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+ CPURISCVState *env = &cpu->env;
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+ bool set_misa_c = false;
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+
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+ if (riscv_has_ext(env, RVC)) {
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+ return;
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+ }
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+
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+ if (cpu->cfg.ext_zca && !riscv_has_ext(env, RVF)) {
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+ set_misa_c = true;
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+ } else if (riscv_cpu_mxl(env) == MXL_RV32 &&
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+ cpu->cfg.ext_zca && cpu->cfg.ext_zcf &&
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+ (riscv_has_ext(env, RVD) ? cpu->cfg.ext_zcd :
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+ riscv_has_ext(env, RVF))) {
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+ set_misa_c = true;
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+ } else if (riscv_cpu_mxl(env) == MXL_RV64 &&
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+ cpu->cfg.ext_zca && cpu->cfg.ext_zcd) {
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+ set_misa_c = true;
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+ }
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+
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+ if (set_misa_c) {
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+ if (cpu_misa_ext_is_user_set(RVC)) {
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+ warn_report("RVC mandated by Zca/Zcf/Zcd extensions");
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+ return;
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+ }
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+
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+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVC);
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+ }
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+}
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+
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void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
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{
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CPURISCVState *env = &cpu->env;
@@ -1170,6 +1208,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
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riscv_cpu_init_implied_exts_rules();
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riscv_cpu_enable_implied_rules(cpu);
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+ riscv_cpu_update_misa_c(cpu);
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riscv_cpu_validate_misa_priv(env, &local_err);
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if (local_err != NULL) {