target/arm: migrate basic syndrome helpers to registerfields
We have a registerfields interface which we can use for defining fields alongside helpers to access them. Define the basic syndrome layout and convert the helpers that take the imm16 data directly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20260422125250.1303100-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée committed
Apr 22, 2026 at 13:52 UTC
f0b64ba2bc1d0d026775a3a06ed419c6b8b4808c
1 file changed
+57
-18
target/arm/syndrome.h
+57
-18
@@ -25,7 +25,7 @@
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#ifndef TARGET_ARM_SYNDROME_H
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#define TARGET_ARM_SYNDROME_H
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-#include "qemu/bitops.h"
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+#include "hw/core/registerfields.h"
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/* Valid Syndrome Register EC field values */
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enum arm_exception_class {
@@ -76,6 +76,11 @@ enum arm_exception_class {
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EC_AA64_BKPT = 0x3c,
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};
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+/* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */
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+FIELD(SYNDROME, EC, 26, 6)
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+FIELD(SYNDROME, IL, 25, 1)
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+FIELD(SYNDROME, ISS, 0, 25)
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+
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typedef enum {
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SME_ET_AccessTrap,
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SME_ET_Streaming,
@@ -113,12 +118,12 @@ typedef enum {
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static inline uint32_t syn_get_ec(uint32_t syn)
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{
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- return syn >> ARM_EL_EC_SHIFT;
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+ return FIELD_EX32(syn, SYNDROME, EC);
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}
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static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)
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{
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- return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec);
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+ return FIELD_DP32(syn, SYNDROME, EC, ec);
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}
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/*
@@ -133,49 +138,74 @@ static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)
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*/
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static inline uint32_t syn_uncategorized(void)
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{
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- return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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+ uint32_t res = syn_set_ec(0, EC_UNCATEGORIZED);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ return res;
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}
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+FIELD(ISS_IMM16, IMM16, 0, 16)
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+
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static inline uint32_t syn_aa64_svc(uint32_t imm16)
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{
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- return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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+ uint32_t res = syn_set_ec(0, EC_AA64_SVC);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);
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+ return res;
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}
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static inline uint32_t syn_aa64_hvc(uint32_t imm16)
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{
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- return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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+ uint32_t res = syn_set_ec(0, EC_AA64_HVC);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);
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+ return res;
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}
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static inline uint32_t syn_aa64_smc(uint32_t imm16)
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{
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- return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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+ uint32_t res = syn_set_ec(0, EC_AA64_SMC);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);
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+ return res;
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}
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static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
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{
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- return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
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- | (is_16bit ? 0 : ARM_EL_IL);
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+ uint32_t res = syn_set_ec(0, EC_AA32_SVC);
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+ res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);
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+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);
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+ return res;
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}
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static inline uint32_t syn_aa32_hvc(uint32_t imm16)
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{
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- return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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+ uint32_t res = syn_set_ec(0, EC_AA32_HVC);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);
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+ return res;
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}
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static inline uint32_t syn_aa32_smc(void)
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{
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- return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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+ uint32_t res = syn_set_ec(0, EC_AA32_SMC);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ return res;
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}
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static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
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{
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- return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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+ uint32_t res = syn_set_ec(0, EC_AA64_BKPT);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);
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+ return res;
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}
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static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
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{
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- return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
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- | (is_16bit ? 0 : ARM_EL_IL);
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+ uint32_t res = syn_set_ec(0, EC_AA32_BKPT);
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+ res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);
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+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);
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+ return res;
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}
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static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
@@ -246,7 +276,9 @@ static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
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static inline uint32_t syn_sve_access_trap(void)
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{
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- return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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+ uint32_t res = syn_set_ec(0, EC_SVEACCESSTRAP);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ return res;
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}
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/*
@@ -361,12 +393,16 @@ static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
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static inline uint32_t syn_illegalstate(void)
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{
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- return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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+ uint32_t res = syn_set_ec(0, EC_ILLEGALSTATE);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ return res;
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}
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static inline uint32_t syn_pcalignment(void)
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{
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- return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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+ uint32_t res = syn_set_ec(0, EC_PCALIGNMENT);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ return res;
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}
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static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn)
@@ -388,7 +424,10 @@ static inline uint32_t syn_gcs_gcsstr(int ra, int rn)
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static inline uint32_t syn_serror(uint32_t extra)
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{
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- return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
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+ uint32_t res = syn_set_ec(0, EC_SERROR);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ res = FIELD_DP32(res, SYNDROME, ISS, extra);
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+ return res;
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}
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static inline uint32_t syn_mop(bool is_set, bool is_setg, int options,