@samitouri / QOSamiQemu / commits / f35f0f1ca1

hw/intc/arm_gicv3: Fix NS write to ICC_AP1Rn_EL1 when prebits < 7

The existing code uses a blanket `regno < 2` check to make ICC_AP1R0_EL1 and ICC_AP1R1_EL1 writes from Non-secure code WI (Write Ignore) when EL3 is present. This is intended to prevent NS code from claiming active interrupts in the Secure priority range, which could block Secure interrupt delivery. However, that check assumes prebits=7 (4 APR registers), where the NS priority range (128..255) maps entirely to AP1R2/AP1R3. Since commit 39f29e599355 ("hw/intc/arm_gicv3: Use correct number of priority bits for the CPU", first in 7.1), all QEMU AArch64 CPUs are initialised with gic_pribits=5 (one APR register), so NS priorities map to AP1R0 bits [16:31]. Blanket WI of the entire AP1R0 register prevents NS code from clearing its own NS active priority bits. Machines using hw_compat_7_0 (e.g. virt-7.0) still force pribits=8 via force-8-bit-prio and are therefore unaffected. A concrete consequence observed in virtualisation scenarios: when a guest VM acknowledges an SPI interrupt but does not perform EOI, is force-killed and restarted, the new guest's attempt to clear the residual active state by writing ICC_AP1R0_EL1=0 is silently ignored. The running priority (RPR) remains stuck at the old interrupt's priority, preventing all equal-or-lower priority interrupts (including timer interrupts) from being delivered, and hanging the guest. Fix this by computing the exact Secure/NS boundary within the APR bank based on prebits. For registers entirely in the Secure range, keep the WI behaviour. For the register that straddles the boundary, preserve only the Secure bits while allowing NS bits to be modified. For registers entirely in the NS range, allow full write access. The new logic produces identical behaviour to the old code when prebits=7, preserving existing behaviour for machines that use force-8-bit-prio. Fixes: 39f29e599355 ("hw/intc/arm_gicv3: Use correct number of priority bits for the CPU") Cc: qemu-stable@nongnu.org Signed-off-by: liugan1 <liugan1@lixiang.com> Message-id: 20260428083119.1400110-1-gs_liugan@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

liugan1 committed May 5, 2026 at 09:25 UTC f35f0f1ca121fb4931fe98570cda3aeb06b7a87f

1 file changed +33 -2

hw/intc/arm_gicv3_cpuif.c

+33 -2

@@ -1869,9 +1869,40 @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,

1869 * at a priority outside the Non-secure range (128..255), since this

1870 * would otherwise allow malicious NS code to block delivery of S interrupts

1871 * by writing a bad value to these registers.

1872 + *

1873 + * The NS priority range (128..255) maps to APR bits starting at

1874 + * aprbit = 0x80 >> (8 - prebits). Depending on prebits, this boundary

1875 + * may fall within AP1R0 or AP1R1, so we cannot simply WI the entire

1876 + * register. Instead we calculate which bits within each register

1877 + * correspond to the Secure range and preserve those, while allowing

1878 + * NS code to modify only the NS range bits.

1879 + *

1880 + * prebits=4: num_aprs=1, NS starts at AP1R0[8]

1881 + * prebits=5: num_aprs=1, NS starts at AP1R0[16]

1882 + * prebits=6: num_aprs=2, NS starts at AP1R1[0]

1883 + * prebits=7: num_aprs=4, NS starts at AP1R2[0]

1884 */

1873 - if (grp == GICV3_G1NS && regno < 2 && arm_feature(env, ARM_FEATURE_EL3)) {

1874 - return;

1885 + if (grp == GICV3_G1NS && arm_feature(env, ARM_FEATURE_EL3)) {

1886 + int ns_start_bit = 0x80 >> (8 - cs->prebits);

1887 + int ns_start_regno = ns_start_bit / 32;

1888 + int ns_start_regbit = ns_start_bit % 32;

1889 +

1890 + if (regno < ns_start_regno) {

1891 + /* This entire register is in the Secure range: WI */

1892 + return;

1893 + } else if (regno == ns_start_regno && ns_start_regbit > 0) {

1894 + /*

1895 + * This register is split: low bits are Secure, high bits are NS.

1896 + * Preserve the Secure bits (below ns_start_regbit) from the

1897 + * current value, and take the NS bits (at and above

1898 + * ns_start_regbit) from the written value.

1899 + */

1900 + uint32_t secure_mask = MAKE_64BIT_MASK(0, ns_start_regbit);

1901 +

1902 + value = (cs->icc_apr[grp][regno] & secure_mask) |

1903 + (value & ~secure_mask);

1904 + }

1905 + /* else: regno > ns_start_regno, entire register is NS: allow write */

1906 }

1907

1908 if (cs->nmi_support) {