target/mips: add Octeon VMM0 instruction
VMM0 multiplies MPL[0] by rs, adds rt and the queued P[0] partial product, returns the low result, and feeds that result back into MPL[0]. It sets MPL[1] to zero and clears partial products. Include hardware-backed regression coverage for VMM0 MPL1 zeroing. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-22-philmd@linaro.org>
James Hilliard committed
May 8, 2026 at 10:55 UTC
f527390c33031eda5a89351e9b23ffd2306e59d6
3 files changed
+72
target/mips/tcg/octeon.decode
+1
@@ -56,6 +56,7 @@ MTP1 011100 ..... ..... 00000 00000 001010 @r2
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MTP2 011100 ..... ..... 00000 00000 001011 @r2
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VMULU 011100 ..... ..... ..... 00000 001111 @r3
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+VMM0 011100 ..... ..... ..... 00000 010000 @r3
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&saa base rt
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@saa ...... base:5 rt:5 ................ &saa
target/mips/tcg/octeon_translate.c
+16
@@ -299,3 +299,19 @@ static bool trans_VMULU(DisasContext *ctx, arg_VMULU *a)
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gen_store_gpr(tmp, a->rd);
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return true;
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}
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+
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+static bool trans_VMM0(DisasContext *ctx, arg_VMM0 *a)
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+{
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+ TCGv_i64 tmp = tcg_temp_new_i64();
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+
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+ gen_load_gpr(tmp, a->rs);
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+ tcg_gen_mul_i64(oct_mpl[0], oct_mpl[0], tmp);
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+ gen_load_gpr(tmp, a->rt);
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+ tcg_gen_add_i64(oct_mpl[0], oct_mpl[0], tmp);
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+ tcg_gen_add_i64(oct_mpl[0], oct_mpl[0], oct_p[0]);
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+ gen_store_gpr(oct_mpl[0], a->rd);
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+
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+ tcg_gen_movi_i64(oct_mpl[1], 0);
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+ octeon_zero_partial_product_state();
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+ return true;
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+}
tests/tcg/mips/user/isa/octeon/octeon-insns.c
+55
@@ -105,6 +105,59 @@ static uint64_t octeon_vmulu(uint64_t mpl0, uint64_t rs, uint64_t rt)
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return rd;
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}
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+static uint64_t octeon_vmm0(uint64_t mpl0, uint64_t p0,
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+ uint64_t rs, uint64_t rt)
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+{
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+ uint64_t rd;
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+
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+ asm volatile(
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+ "move $8, %[mpl0]\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x71090008\n\t" /* mtm0 $8, $9 */
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+ "move $8, %[p0]\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x71090009\n\t" /* mtp0 $8, $9 */
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+ "move $8, %[rs]\n\t"
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+ "move $9, %[rt]\n\t"
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+ ".word 0x71095010\n\t" /* vmm0 $10, $8, $9 */
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+ "move %[rd], $10\n\t"
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+ : [rd] "=r" (rd)
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+ : [mpl0] "r" (mpl0), [p0] "r" (p0),
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+ [rs] "r" (rs), [rt] "r" (rt)
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+ : "$8", "$9", "$10");
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+
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+ return rd;
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+}
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+
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+static uint64_t octeon_vmm0_zeroes_mpl1(void)
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+{
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+ uint64_t rd;
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+
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+ asm volatile(
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+ "move $8, %[mpl0]\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x71090008\n\t" /* mtm0 $8, $9 */
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+ "move $8, %[mpl1]\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x7109000c\n\t" /* mtm1 $8, $9 */
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+ "move $8, %[vmm0_rs]\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x71095010\n\t" /* vmm0 $10, $8, $9 */
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+ "move $8, %[vmulu_rs]\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */
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+ "move $8, $0\n\t"
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+ "move $9, $0\n\t"
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+ ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */
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+ "move %[rd], $10\n\t"
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+ : [rd] "=r" (rd)
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+ : [mpl0] "r" (1ULL), [mpl1] "r" (1ULL),
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+ [vmm0_rs] "r" (2ULL), [vmulu_rs] "r" (1ULL)
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+ : "$8", "$9", "$10");
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+
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+ return rd;
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+}
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+
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static uint64_t octeon_mtp0_zeroes_p1(void)
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{
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uint64_t rd;
@@ -143,6 +196,8 @@ int main(void)
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assert(octeon_sne(0xabc, 0xabc) == 0);
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assert(octeon_sne(0xabc, 0xdef) == 1);
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assert(octeon_vmulu(5, 7, 11) == 46);
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+ assert(octeon_vmm0(5, 13, 7, 11) == 59);
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+ assert(octeon_vmm0_zeroes_mpl1() == 0);
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assert(octeon_mtp0_zeroes_p1() == 0);
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return 0;