hw/arm/fsl-imx8mm: Adding support for SPI controller
It enables emulation of ECSPI in iMX8MM Added SPI IRQ lines Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gaurav Sharma committed
Apr 21, 2026 at 12:22 UTC
f5689c7ef31481251cab78f9ea271addc900775a
2 files changed
+33
hw/arm/fsl-imx8mm.c
+26
@@ -195,6 +195,11 @@ static void fsl_imx8mm_init(Object *obj)
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object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
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}
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+ for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {
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+ g_autofree char *name = g_strdup_printf("spi%d", i + 1);
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+ object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
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+ }
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+
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object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
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object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
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TYPE_FSL_IMX8M_PCIE_PHY);
@@ -464,6 +469,26 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
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qdev_get_gpio_in(gicdev, usdhc_table[i].irq));
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}
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+ /* ECSPIs */
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+ for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {
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+ static const struct {
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+ hwaddr addr;
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+ unsigned int irq;
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+ } spi_table[FSL_IMX8MM_NUM_ECSPIS] = {
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+ { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI1].addr, FSL_IMX8MM_ECSPI1_IRQ },
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+ { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI2].addr, FSL_IMX8MM_ECSPI2_IRQ },
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+ { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI3].addr, FSL_IMX8MM_ECSPI3_IRQ },
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+ };
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+
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+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
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+ return;
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+ }
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+
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+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
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+ qdev_get_gpio_in(gicdev, spi_table[i].irq));
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+ }
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+
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/* SNVS */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {
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return;
@@ -503,6 +528,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
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case FSL_IMX8MM_GIC_DIST:
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case FSL_IMX8MM_GIC_REDIST:
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case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:
531
+ case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3:
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case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4:
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case FSL_IMX8MM_PCIE1:
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case FSL_IMX8MM_PCIE_PHY1:
include/hw/arm/fsl-imx8mm.h
+7
@@ -21,6 +21,7 @@
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#include "hw/pci-host/designware.h"
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#include "hw/pci-host/fsl_imx8m_phy.h"
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#include "hw/sd/sdhci.h"
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+#include "hw/ssi/imx_spi.h"
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#include "qom/object.h"
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#include "qemu/units.h"
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@@ -32,6 +33,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)
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enum FslImx8mmConfiguration {
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FSL_IMX8MM_NUM_CPUS = 4,
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+ FSL_IMX8MM_NUM_ECSPIS = 3,
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FSL_IMX8MM_NUM_GPIOS = 5,
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FSL_IMX8MM_NUM_I2CS = 4,
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FSL_IMX8MM_NUM_IRQS = 128,
@@ -48,6 +50,7 @@ struct FslImx8mmState {
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IMX8MPCCMState ccm;
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IMX8MPAnalogState analog;
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IMX7SNVSState snvs;
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+ IMXSPIState spi[FSL_IMX8MM_NUM_ECSPIS];
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IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS];
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IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];
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MemoryRegion ocram;
@@ -177,6 +180,10 @@ enum FslImx8mmIrqs {
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FSL_IMX8MM_UART3_IRQ = 28,
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FSL_IMX8MM_UART4_IRQ = 29,
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+ FSL_IMX8MM_ECSPI1_IRQ = 31,
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+ FSL_IMX8MM_ECSPI2_IRQ = 32,
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+ FSL_IMX8MM_ECSPI3_IRQ = 33,
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+
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FSL_IMX8MM_I2C1_IRQ = 35,
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FSL_IMX8MM_I2C2_IRQ = 36,
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FSL_IMX8MM_I2C3_IRQ = 37,