target/riscv: remove riscv_cpu_named_features[]
This array has no uses left. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260512032926.1978818-8-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
May 12, 2026 at 00:29 UTC
f8d4df547594f7da94ebdb4ec5ddb759d65283e4
3 files changed
+2
-29
target/riscv/cpu.c
-26
@@ -1411,32 +1411,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
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{ },
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};
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-/*
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- * 'Named features' is the name we give to extensions that we
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- * don't want to expose to users. They are either immutable
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- * (always enabled/disable) or they'll vary depending on
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- * the resulting CPU state.
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- *
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- * Some of them are always enabled depending on priv version
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- * of the CPU and are declared directly in isa_edata_arr[].
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- * The ones listed here have special checks during finalize()
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- * time and require their own flags like regular extensions.
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- * See riscv_cpu_update_named_features() for more info.
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- */
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-const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
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- MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
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- MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
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- MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
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-
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- /*
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- * 'ziccrse' has its own flag because the KVM driver
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- * wants to enable/disable it on its own accord.
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- */
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- MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true),
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-
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- { },
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-};
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-
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static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname,
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Error **errp)
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{
target/riscv/cpu.h
-1
@@ -992,7 +992,6 @@ typedef struct RISCVCPUMultiExtConfig {
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extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
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extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
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extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
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-extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[];
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typedef struct isa_ext_data {
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const char *name;
target/riscv/tcg/tcg-cpu.c
+2
-2
@@ -454,7 +454,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
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}
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}
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-static void riscv_cpu_update_named_features(RISCVCPU *cpu)
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+static void riscv_cpu_update_cfg(RISCVCPU *cpu)
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{
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if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) {
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cpu->cfg.has_priv_1_11 = true;
@@ -1181,7 +1181,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
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return;
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}
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- riscv_cpu_update_named_features(cpu);
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+ riscv_cpu_update_cfg(cpu);
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riscv_cpu_validate_profiles(cpu);
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if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {