tests/qtest: Add Intel IOMMU bare-metal test
Add a qtest suite for the Intel IOMMU (VT-d) device on the Q35 machine. The test exercises both Legacy and Scalable translation modes using iommu-testdev and the qos-intel-iommu helpers, without requiring any guest kernel or firmware. The test validates: - Legacy-mode Root Entry Table and Context Entry Table configuration - Scalable-mode Context Entry, PASID Directory, and PASID Table setup - Legacy-mode 4-level page table walks for 48-bit address translation - Scalable-mode second-level and first-level 4-level page table walks - Pass-through mode in both Legacy and Scalable modes - DMA transaction execution with memory content verification Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Signed-off-by: Fengyuan Yu <15fengyuan@gmail.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Tao Tang <tangtao1634@phytium.com.cn> Link: https://lore.kernel.org/qemu-devel/ce3c44f3b07734a4f0ee43f55b21c856034af1b1.1774421649.git.15fengyuan@gmail.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
Fengyuan Yu committed
Mar 25, 2026 at 15:09 UTC
f95eeea5c85bd197077e1ce3f5df61f95ea8ebe5
3 files changed
+219
MAINTAINERS
+1
@@ -4010,6 +4010,7 @@ F: hw/i386/intel_iommu_accel.*
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F: include/hw/i386/intel_iommu.h
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F: tests/functional/x86_64/test_intel_iommu.py
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F: tests/qtest/intel-iommu-test.c
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+F: tests/qtest/iommu-intel-test.c
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AMD-Vi Emulation
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M: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
tests/qtest/iommu-intel-test.c
new
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@@ -0,0 +1,216 @@
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+/*
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+ * QTest for Intel IOMMU (VT-d) with iommu-testdev
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+ *
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+ * This QTest file is used to test the Intel IOMMU with iommu-testdev so that
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+ * we can test VT-d without any guest kernel or firmware.
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+ *
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+ * Copyright (c) 2026 Fengyuan Yu <15fengyuan@gmail.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "libqtest.h"
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+#include "libqos/pci.h"
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+#include "libqos/pci-pc.h"
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+#include "hw/i386/intel_iommu_internal.h"
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+#include "hw/misc/iommu-testdev.h"
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+#include "libqos/qos-intel-iommu.h"
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+
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+#define DMA_LEN 4
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+
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+static uint64_t intel_iommu_expected_gpa(uint64_t iova)
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+{
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+ return (QVTD_PT_VAL & VTD_PAGE_MASK_4K) + (iova & 0xfff);
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+}
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+
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+static void save_fn(QPCIDevice *dev, int devfn, void *data)
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+{
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+ QPCIDevice **pdev = (QPCIDevice **) data;
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+
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+ *pdev = dev;
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+}
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+
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+static QPCIDevice *setup_qtest_pci_device(QTestState *qts, QPCIBus **pcibus,
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+ QPCIBar *bar)
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+{
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+ QPCIDevice *dev = NULL;
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+
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+ *pcibus = qpci_new_pc(qts, NULL);
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+ g_assert(*pcibus != NULL);
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+
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+ qpci_device_foreach(*pcibus, IOMMU_TESTDEV_VENDOR_ID,
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+ IOMMU_TESTDEV_DEVICE_ID, save_fn, &dev);
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+
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+ g_assert(dev);
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+ qpci_device_enable(dev);
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+ *bar = qpci_iomap(dev, 0, NULL);
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+ g_assert_false(bar->is_io);
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+
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+ return dev;
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+}
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+
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+static const char *qvtd_iommu_args(QVTDTransMode mode)
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+{
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+ switch (mode) {
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+ case QVTD_TM_SCALABLE_FLT:
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+ return "-device intel-iommu,x-scalable-mode=on,x-flts=on ";
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+ case QVTD_TM_SCALABLE_PT:
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+ case QVTD_TM_SCALABLE_SLT:
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+ return "-device intel-iommu,x-scalable-mode=on ";
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+ default:
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+ return "-device intel-iommu ";
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+ }
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+}
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+
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+static bool qvtd_check_caps(QTestState *qts, QVTDTransMode mode)
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+{
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+ uint64_t ecap = qtest_readq(qts,
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+ Q35_HOST_BRIDGE_IOMMU_ADDR + DMAR_ECAP_REG);
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+
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+ /* All scalable modes require SMTS */
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+ if (qvtd_is_scalable(mode) && !(ecap & VTD_ECAP_SMTS)) {
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+ g_test_skip("ECAP.SMTS not supported");
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+ return false;
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+ }
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+
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+ switch (mode) {
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+ case QVTD_TM_SCALABLE_PT:
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+ if (!(ecap & VTD_ECAP_PT)) {
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+ g_test_skip("ECAP.PT not supported");
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+ return false;
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+ }
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+ break;
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+ case QVTD_TM_SCALABLE_SLT:
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+ if (!(ecap & VTD_ECAP_SSTS)) {
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+ g_test_skip("ECAP.SSTS not supported");
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+ return false;
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+ }
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+ break;
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+ case QVTD_TM_SCALABLE_FLT:
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+ if (!(ecap & VTD_ECAP_FSTS)) {
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+ g_test_skip("ECAP.FSTS not supported");
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+ return false;
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+ }
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ return true;
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+}
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+
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+static void run_intel_iommu_translation(const QVTDTestConfig *cfg)
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+{
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+ QTestState *qts;
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+ QPCIBus *pcibus;
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+ QPCIDevice *dev;
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+ QPCIBar bar;
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+
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+ if (!qtest_has_machine("q35")) {
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+ g_test_skip("q35 machine not available");
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+ return;
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+ }
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+
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+ /* Initialize QEMU environment for Intel IOMMU testing */
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+ qts = qtest_initf("-machine q35 -smp 1 -m 512 -net none "
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+ "%s -device iommu-testdev",
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+ qvtd_iommu_args(cfg->trans_mode));
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+
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+ /* Check CAP/ECAP capabilities for required translation mode */
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+ if (!qvtd_check_caps(qts, cfg->trans_mode)) {
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+ qtest_quit(qts);
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+ return;
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+ }
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+
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+ /* Setup and configure IOMMU-testdev PCI device */
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+ dev = setup_qtest_pci_device(qts, &pcibus, &bar);
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+ g_assert(dev);
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+
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+ g_test_message("### Intel IOMMU translation mode=%d ###", cfg->trans_mode);
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+ qvtd_run_translation_case(qts, dev, bar, Q35_HOST_BRIDGE_IOMMU_ADDR, cfg);
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+ g_free(dev);
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+ qpci_free_pc(pcibus);
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+ qtest_quit(qts);
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+}
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+
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+static void test_intel_iommu_legacy_pt(void)
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+{
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+ QVTDTestConfig cfg = {
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+ .trans_mode = QVTD_TM_LEGACY_PT,
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+ .dma_gpa = QVTD_IOVA, /* pass-through: GPA == IOVA */
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+ .dma_len = DMA_LEN,
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+ .expected_result = 0,
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+ };
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+
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+ run_intel_iommu_translation(&cfg);
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+}
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+
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+static void test_intel_iommu_legacy_trans(void)
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+{
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+ QVTDTestConfig cfg = {
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+ .trans_mode = QVTD_TM_LEGACY_TRANS,
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+ .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),
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+ .dma_len = DMA_LEN,
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+ .expected_result = 0,
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+ };
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+
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+ run_intel_iommu_translation(&cfg);
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+}
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+
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+static void test_intel_iommu_scalable_pt(void)
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+{
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+ QVTDTestConfig cfg = {
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+ .trans_mode = QVTD_TM_SCALABLE_PT,
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+ .dma_gpa = QVTD_IOVA, /* pass-through: GPA == IOVA */
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+ .dma_len = DMA_LEN,
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+ .expected_result = 0,
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+ };
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+
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+ run_intel_iommu_translation(&cfg);
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+}
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+
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+static void test_intel_iommu_scalable_slt(void)
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+{
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+ QVTDTestConfig cfg = {
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+ .trans_mode = QVTD_TM_SCALABLE_SLT,
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+ .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),
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+ .dma_len = DMA_LEN,
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+ .expected_result = 0,
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+ };
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+
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+ run_intel_iommu_translation(&cfg);
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+}
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+
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+static void test_intel_iommu_scalable_flt(void)
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+{
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+ QVTDTestConfig cfg = {
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+ .trans_mode = QVTD_TM_SCALABLE_FLT,
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+ .dma_gpa = intel_iommu_expected_gpa(QVTD_IOVA),
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+ .dma_len = DMA_LEN,
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+ .expected_result = 0,
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+ };
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+
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+ run_intel_iommu_translation(&cfg);
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+}
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+
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+int main(int argc, char **argv)
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+{
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+ g_test_init(&argc, &argv, NULL);
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+
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+ /* Legacy mode tests */
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+ qtest_add_func("/iommu-testdev/intel/legacy-pt",
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+ test_intel_iommu_legacy_pt);
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+ qtest_add_func("/iommu-testdev/intel/legacy-trans",
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+ test_intel_iommu_legacy_trans);
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+
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+ /* Scalable mode tests */
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+ qtest_add_func("/iommu-testdev/intel/scalable-pt",
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+ test_intel_iommu_scalable_pt);
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+ qtest_add_func("/iommu-testdev/intel/scalable-slt",
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+ test_intel_iommu_scalable_slt);
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+ qtest_add_func("/iommu-testdev/intel/scalable-flt",
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+ test_intel_iommu_scalable_flt);
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+
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+ return g_test_run();
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+}
tests/qtest/meson.build
+2
@@ -96,6 +96,8 @@ qtests_i386 = \
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(config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] : []) + \
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(config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) + \
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(config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) + \
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+ (config_all_devices.has_key('CONFIG_VTD') and
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+ config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') ? ['iommu-intel-test'] : []) + \
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(host_os != 'windows' and \
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config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + \
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(config_all_devices.has_key('CONFIG_PCIE_PORT') and \