whpx: i386: interrupt priority support
Implement APIC IRR interrupt priorities. Even with kernel-irqchip=off, Hyper-V is aware of interrupt priorities and implements CR8/TPR, with the InterruptPriority field being followed. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Link: https://lore.kernel.org/r/20260422214225.2242-14-mohamed@unpredictable.fr Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Mohamed Mediouni committed
Apr 22, 2026 at 23:42 UTC
fad1e8a98e755b6a8ff5edfcadabed1d5b3dc601
1 file changed
+20
-4
target/i386/whpx/whpx-all.c
+20
-4
@@ -1673,6 +1673,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
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UINT32 reg_count = 0;
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WHV_REGISTER_VALUE reg_values[3];
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WHV_REGISTER_NAME reg_names[3];
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+ int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);
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memset(&new_int, 0, sizeof(new_int));
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memset(reg_values, 0, sizeof(reg_values));
@@ -1708,10 +1709,20 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
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}
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}
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+ if (irr == -1) {
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+ if (isa_pic != NULL && pic_get_output(isa_pic)) {
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+ /* In case it's a PIC interrupt */
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+ irr = 0;
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+ } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {
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+ abort();
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+ }
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+ }
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+
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/* Get pending hard interruption or replay one that was overwritten */
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if (!whpx_irqchip_in_kernel()) {
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if (!vcpu->interruption_pending &&
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- vcpu->interruptable && (env->eflags & IF_MASK)) {
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+ vcpu->interruptable && (env->eflags & IF_MASK)
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+ && (vcpu->tpr < irr || irr == 0)) {
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assert(!new_int.InterruptionPending);
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if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {
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cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
@@ -1768,13 +1779,17 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
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}
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/* Update the state of the interrupt delivery notification */
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- if (!vcpu->window_registered &&
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+ if ((!vcpu->window_registered ||
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+ (vcpu->window_priority < irr && vcpu->window_priority != 0) ||
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+ (irr == 0 && vcpu->window_priority != 0)) &&
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cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {
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reg_values[reg_count].DeliverabilityNotifications =
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(WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) {
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- .InterruptNotification = 1
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+ .InterruptNotification = 1,
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+ .InterruptPriority = irr >> 4
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};
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vcpu->window_registered = 1;
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+ vcpu->window_priority = irr;
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reg_names[reg_count] = WHvX64RegisterDeliverabilityNotifications;
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reg_count += 1;
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}
@@ -1788,7 +1803,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
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reg_names, reg_count, reg_values);
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if (FAILED(hr)) {
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error_report("WHPX: Failed to set interrupt state registers,"
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- " hr=%08lx", hr);
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+ " hr=%08lx, InterruptPriority=%i", hr, irr >> 4);
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}
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}
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}
@@ -2004,6 +2019,7 @@ int whpx_vcpu_run(CPUState *cpu)
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case WHvRunVpExitReasonX64InterruptWindow:
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vcpu->ready_for_pic_interrupt = 1;
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vcpu->window_registered = 0;
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+ vcpu->window_priority = 0;
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ret = 0;
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break;
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