| 1 | /* |
| 2 | * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #pragma once |
| 18 | |
| 19 | namespace vllm { |
| 20 | namespace cuda_async { |
| 21 | |
| 22 | __device__ __forceinline__ void cp_async_shared_global_16_cg( |
| 23 | void* smem_ptr, const void* glob_ptr) { |
| 24 | #if defined(USE_ROCM) |
| 25 | *reinterpret_cast<int4*>(smem_ptr) = *reinterpret_cast<const int4*>(glob_ptr); |
| 26 | #elif defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800 |
| 27 | uint32_t smem = static_cast<uint32_t>(__cvta_generic_to_shared(smem_ptr)); |
| 28 | asm volatile("cp.async.cg.shared.global [%0], [%1], 16;\n" |
| 29 | : |
| 30 | : "r"(smem), "l"(glob_ptr)); |
| 31 | #elif defined(__CUDA_ARCH__) |
| 32 | *reinterpret_cast<int4*>(smem_ptr) = *reinterpret_cast<const int4*>(glob_ptr); |
| 33 | #else |
| 34 | (void)smem_ptr; |
| 35 | (void)glob_ptr; |
| 36 | #endif |
| 37 | } |
| 38 | |
| 39 | __device__ __forceinline__ void cp_async_shared_global_ca(void* smem_ptr, |
| 40 | const void* glob_ptr, |
| 41 | int size_bytes) { |
| 42 | #if defined(USE_ROCM) |
| 43 | if (size_bytes == 4) { |
| 44 | *reinterpret_cast<uint32_t*>(smem_ptr) = |
| 45 | *reinterpret_cast<const uint32_t*>(glob_ptr); |
| 46 | } else if (size_bytes == 8) { |
| 47 | *reinterpret_cast<uint64_t*>(smem_ptr) = |
| 48 | *reinterpret_cast<const uint64_t*>(glob_ptr); |
| 49 | } else { |
| 50 | *reinterpret_cast<int4*>(smem_ptr) = |
| 51 | *reinterpret_cast<const int4*>(glob_ptr); |
| 52 | } |
| 53 | #elif defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800 |
| 54 | uint32_t smem = static_cast<uint32_t>(__cvta_generic_to_shared(smem_ptr)); |
| 55 | if (size_bytes == 4) { |
| 56 | asm volatile("cp.async.ca.shared.global [%0], [%1], 4;\n" |
| 57 | : |
| 58 | : "r"(smem), "l"(glob_ptr)); |
| 59 | } else if (size_bytes == 8) { |
| 60 | asm volatile("cp.async.ca.shared.global [%0], [%1], 8;\n" |
| 61 | : |
| 62 | : "r"(smem), "l"(glob_ptr)); |
| 63 | } else { |
| 64 | asm volatile("cp.async.ca.shared.global [%0], [%1], 16;\n" |
| 65 | : |
| 66 | : "r"(smem), "l"(glob_ptr)); |
| 67 | } |
| 68 | #elif defined(__CUDA_ARCH__) |
| 69 | if (size_bytes == 4) { |
| 70 | *reinterpret_cast<uint32_t*>(smem_ptr) = |
| 71 | *reinterpret_cast<const uint32_t*>(glob_ptr); |
| 72 | } else if (size_bytes == 8) { |
| 73 | *reinterpret_cast<uint64_t*>(smem_ptr) = |
| 74 | *reinterpret_cast<const uint64_t*>(glob_ptr); |
| 75 | } else { |
| 76 | *reinterpret_cast<int4*>(smem_ptr) = |
| 77 | *reinterpret_cast<const int4*>(glob_ptr); |
| 78 | } |
| 79 | #else |
| 80 | (void)smem_ptr; |
| 81 | (void)glob_ptr; |
| 82 | (void)size_bytes; |
| 83 | #endif |
| 84 | } |
| 85 | |
| 86 | __device__ __forceinline__ void cp_async_commit_group() { |
| 87 | #if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800 && !defined(USE_ROCM) |
| 88 | asm volatile("cp.async.commit_group;\n" ::); |
| 89 | #endif |
| 90 | } |
| 91 | |
| 92 | template <int n> |
| 93 | __device__ __forceinline__ void cp_async_wait_group() { |
| 94 | #if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800 && !defined(USE_ROCM) |
| 95 | asm volatile("cp.async.wait_group %0;\n" : : "n"(n)); |
| 96 | #endif |
| 97 | } |
| 98 | |
| 99 | } // namespace cuda_async |
| 100 | } // namespace vllm |