| 1 | /* |
| 2 | * SPDX-License-Identifier: Apache-2.0 |
| 3 | * SPDX-FileCopyrightText: Copyright contributors to the vLLM project |
| 4 | * |
| 5 | * MXFP4 activation quantization kernel for MoE experts. |
| 6 | * Quantizes BF16/FP16 activations to MXFP4: E2M1 values with E8M0 block scales |
| 7 | * over 32-element groups. |
| 8 | * |
| 9 | * Uses PACK16 E2M1 conversion helpers (nvfp4_utils.cuh) configured for: |
| 10 | * - Block size 32 (2 threads per SF in PACK16 mode) |
| 11 | * - E8M0 (power-of-two) scale factors |
| 12 | * - SF layout: [numMTiles, numKTiles, 32, 4, 4] where numKTiles=ceil(K/128) |
| 13 | */ |
| 14 | |
| 15 | // MXFP4 requires PACK16 mode (16 elements per thread) so that |
| 16 | // 2 threads cover 32-element blocks. This requires CUDA >= 12.9. |
| 17 | // Must be defined before any header that (transitively) includes |
| 18 | // nvfp4_utils.cuh. |
| 19 | #define NVFP4_ENABLE_ELTS16 1 |
| 20 | |
| 21 | #include <cuda.h> |
| 22 | #include <cuda_runtime_api.h> |
| 23 | #include <cuda_runtime.h> |
| 24 | #include <cuda_fp8.h> |
| 25 | |
| 26 | #include <torch/csrc/stable/library.h> |
| 27 | #include <torch/csrc/stable/tensor.h> |
| 28 | #include "libtorch_stable/torch_utils.h" |
| 29 | #include "libtorch_stable/dispatch_utils.h" |
| 30 | #include "libtorch_stable/cutlass_extensions/common.hpp" |
| 31 | #include "../../cuda_vec_utils.cuh" |
| 32 | #include "cuda_utils.h" |
| 33 | |
| 34 | #include "nvfp4_utils.cuh" |
| 35 | |
| 36 | #if defined(CUDART_VERSION) && CUDART_VERSION >= 12090 |
| 37 | #define VLLM_MXFP4_EXPERTS_QUANT_SUPPORTED 1 |
| 38 | static_assert(CVT_FP4_ELTS_PER_THREAD == 16, |
| 39 | "MXFP4 experts quant requires PACK16 mode (CUDA >= 12.9)"); |
| 40 | #else |
| 41 | #define VLLM_MXFP4_EXPERTS_QUANT_SUPPORTED 0 |
| 42 | #endif |
| 43 | |
| 44 | #include "libtorch_stable/launch_bounds_utils.h" |
| 45 | |
| 46 | #if VLLM_MXFP4_EXPERTS_QUANT_SUPPORTED |
| 47 | |
| 48 | namespace vllm { |
| 49 | |
| 50 | // MXFP4 block size constants |
| 51 | static constexpr int MXFP4_SF_VEC_SIZE = 32; |
| 52 | |
| 53 | // For PACK16 mode (CVT_FP4_ELTS_PER_THREAD=16): 2 threads per SF |
| 54 | // For PACK8 mode (CVT_FP4_ELTS_PER_THREAD=8): 4 threads per SF |
| 55 | static constexpr int MXFP4_NUM_THREADS_PER_SF = |
| 56 | MXFP4_SF_VEC_SIZE / CVT_FP4_ELTS_PER_THREAD; |
| 57 | |
| 58 | // MXFP4 quantization kernel for experts. |
| 59 | // Uses 32-element blocks with E8M0 (UE8M0) scale factors. |
| 60 | // When FUSE_SILU_MUL=true, expects input with gate||up layout and fuses |
| 61 | // SiLU(gate)*up before quantization. |
| 62 | template <class Type, bool FUSE_SILU_MUL = false, |
| 63 | bool SMALL_NUM_EXPERTS = false> |
| 64 | __global__ void __launch_bounds__(512, VLLM_BLOCKS_PER_SM(512)) |
| 65 | mxfp4_cvt_fp16_to_fp4(int32_t numRows, int32_t numCols, Type const* in, |
| 66 | fp4_packed_t* out, uint32_t* SFout, |
| 67 | uint32_t* input_offset_by_experts, |
| 68 | uint32_t* output_scale_offset_by_experts, |
| 69 | int n_experts, bool low_latency) { |
| 70 | using PackedVec = PackedVec<Type, CVT_FP4_PACK16>; |
| 71 | static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD, |
| 72 | "Vec size is not matched."); |
| 73 | |
| 74 | // MXFP4: numKTiles = ceil(numCols / 128) since block_size=32, 4 SFs/tile |
| 75 | int32_t const numKTiles = (numCols + 127) / 128; |
| 76 | |
| 77 | int tid = blockIdx.x * blockDim.x + threadIdx.x; |
| 78 | int colsPerRow = numCols / CVT_FP4_ELTS_PER_THREAD; |
| 79 | int32_t const numValidRows = |
| 80 | min(numRows, |
| 81 | static_cast<int32_t>(__ldca(&input_offset_by_experts[n_experts]))); |
| 82 | int inColsPerRow = FUSE_SILU_MUL ? colsPerRow * 2 : colsPerRow; |
| 83 | |
| 84 | for (int globalIdx = tid; globalIdx < numValidRows * colsPerRow; |
| 85 | globalIdx += gridDim.x * blockDim.x) { |
| 86 | int rowIdx = globalIdx / colsPerRow; |
| 87 | int colIdx = globalIdx % colsPerRow; |
| 88 | |
| 89 | int rowIdx_in_expert = 0; |
| 90 | int expert_idx = 0; |
| 91 | |
| 92 | if constexpr (SMALL_NUM_EXPERTS) { |
| 93 | for (int i = 0; i < n_experts; i++) { |
| 94 | uint32_t current_offset = __ldca(&input_offset_by_experts[i]); |
| 95 | uint32_t next_offset = __ldca(&input_offset_by_experts[i + 1]); |
| 96 | if (rowIdx >= current_offset && rowIdx < next_offset) { |
| 97 | rowIdx_in_expert = rowIdx - current_offset; |
| 98 | expert_idx = i; |
| 99 | break; |
| 100 | } |
| 101 | } |
| 102 | } else { |
| 103 | uint32_t local_offsets[17]; |
| 104 | for (int chunk_start = 0; chunk_start < n_experts; chunk_start += 16) { |
| 105 | *reinterpret_cast<int4*>(local_offsets) = |
| 106 | __ldca(reinterpret_cast<const int4*>( |
| 107 | &input_offset_by_experts[chunk_start])); |
| 108 | *reinterpret_cast<int4*>(local_offsets + 4) = |
| 109 | __ldca(reinterpret_cast<const int4*>( |
| 110 | &input_offset_by_experts[chunk_start + 4])); |
| 111 | *reinterpret_cast<int4*>(local_offsets + 8) = |
| 112 | __ldca(reinterpret_cast<const int4*>( |
| 113 | &input_offset_by_experts[chunk_start + 8])); |
| 114 | *reinterpret_cast<int4*>(local_offsets + 12) = |
| 115 | __ldca(reinterpret_cast<const int4*>( |
| 116 | &input_offset_by_experts[chunk_start + 12])); |
| 117 | local_offsets[16] = __ldca(&input_offset_by_experts[chunk_start + 16]); |
| 118 | |
| 119 | #pragma unroll |
| 120 | for (int i = 0; i < 16; i++) { |
| 121 | if (rowIdx >= local_offsets[i] && rowIdx < local_offsets[i + 1]) { |
| 122 | rowIdx_in_expert = rowIdx - local_offsets[i]; |
| 123 | expert_idx = chunk_start + i; |
| 124 | break; |
| 125 | } |
| 126 | } |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | // Load input and optionally apply fused SiLU+Mul |
| 131 | int64_t inOffset = rowIdx * inColsPerRow + colIdx; |
| 132 | PackedVec in_vec = reinterpret_cast<PackedVec const*>(in)[inOffset]; |
| 133 | PackedVec quant_input; |
| 134 | if constexpr (FUSE_SILU_MUL) { |
| 135 | PackedVec in_vec_up = |
| 136 | reinterpret_cast<PackedVec const*>(in)[inOffset + colsPerRow]; |
| 137 | quant_input = compute_silu_mul(in_vec, in_vec_up); |
| 138 | } else { |
| 139 | quant_input = in_vec; |
| 140 | } |
| 141 | |
| 142 | // In PACK16 mode, each thread outputs 16 E2M1 values = u32x2 |
| 143 | int64_t outOffset = rowIdx * colsPerRow + colIdx; |
| 144 | auto& out_pos = out[outOffset]; |
| 145 | |
| 146 | uint32_t* SFout_in_expert = |
| 147 | SFout + output_scale_offset_by_experts[expert_idx] * numKTiles; |
| 148 | |
| 149 | // Use MXFP4_NUM_THREADS_PER_SF (2 for PACK16) for 32-element blocks |
| 150 | auto sf_out = |
| 151 | cvt_quant_to_fp4_get_sf_out_offset<uint32_t, MXFP4_NUM_THREADS_PER_SF>( |
| 152 | rowIdx_in_expert, colIdx, numKTiles, SFout_in_expert); |
| 153 | |
| 154 | // Block E8M0 scales only; no extra tensor-level scale in this path |
| 155 | constexpr float SFScaleVal = 1.0f; |
| 156 | // UE8M0_SF=true for MXFP4 E8M0 scale factors |
| 157 | out_pos = |
| 158 | cvt_warp_fp16_to_fp4<Type, MXFP4_NUM_THREADS_PER_SF, /*UE8M0_SF=*/true>( |
| 159 | quant_input, SFScaleVal, sf_out); |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | // Large M_topk variant using shared memory for expert offsets |
| 164 | template <class Type, bool FUSE_SILU_MUL = false, |
| 165 | bool SMALL_NUM_EXPERTS = false> |
| 166 | __global__ void __launch_bounds__(1024, VLLM_BLOCKS_PER_SM(1024)) |
| 167 | mxfp4_cvt_fp16_to_fp4(int32_t numRows, int32_t numCols, Type const* in, |
| 168 | fp4_packed_t* out, uint32_t* SFout, |
| 169 | uint32_t* input_offset_by_experts, |
| 170 | uint32_t* output_scale_offset_by_experts, |
| 171 | int n_experts) { |
| 172 | using PackedVec = PackedVec<Type, CVT_FP4_PACK16>; |
| 173 | static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD, |
| 174 | "Vec size is not matched."); |
| 175 | |
| 176 | // MXFP4: numKTiles = ceil(numCols / 128) |
| 177 | int32_t const numKTiles = (numCols + 127) / 128; |
| 178 | |
| 179 | extern __shared__ uint32_t shared_input_offsets[]; |
| 180 | |
| 181 | if constexpr (SMALL_NUM_EXPERTS) { |
| 182 | for (int i = threadIdx.x; i < n_experts + 1; i += blockDim.x) { |
| 183 | shared_input_offsets[i] = input_offset_by_experts[i]; |
| 184 | } |
| 185 | } else { |
| 186 | for (int i = threadIdx.x * 4; i < n_experts; i += blockDim.x * 4) { |
| 187 | *reinterpret_cast<int4*>(&shared_input_offsets[i]) = |
| 188 | *reinterpret_cast<const int4*>(&input_offset_by_experts[i]); |
| 189 | } |
| 190 | if (threadIdx.x == 0) { |
| 191 | shared_input_offsets[n_experts] = input_offset_by_experts[n_experts]; |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | __syncthreads(); |
| 196 | |
| 197 | int tid = blockIdx.x * blockDim.x + threadIdx.x; |
| 198 | int colsPerRow = numCols / CVT_FP4_ELTS_PER_THREAD; |
| 199 | int32_t const numValidRows = |
| 200 | min(numRows, static_cast<int32_t>(shared_input_offsets[n_experts])); |
| 201 | int inColsPerRow = FUSE_SILU_MUL ? colsPerRow * 2 : colsPerRow; |
| 202 | |
| 203 | for (int globalIdx = tid; globalIdx < numValidRows * colsPerRow; |
| 204 | globalIdx += gridDim.x * blockDim.x) { |
| 205 | int rowIdx = globalIdx / colsPerRow; |
| 206 | int colIdx = globalIdx % colsPerRow; |
| 207 | |
| 208 | int rowIdx_in_expert = 0; |
| 209 | int expert_idx = 0; |
| 210 | |
| 211 | // Binary search through experts using shared memory |
| 212 | int left = 0, right = n_experts - 1; |
| 213 | while (left <= right) { |
| 214 | int mid = (left + right) / 2; |
| 215 | uint32_t mid_offset = shared_input_offsets[mid]; |
| 216 | uint32_t next_offset = shared_input_offsets[mid + 1]; |
| 217 | |
| 218 | if (rowIdx >= mid_offset && rowIdx < next_offset) { |
| 219 | rowIdx_in_expert = rowIdx - mid_offset; |
| 220 | expert_idx = mid; |
| 221 | break; |
| 222 | } else if (rowIdx < mid_offset) { |
| 223 | right = mid - 1; |
| 224 | } else { |
| 225 | left = mid + 1; |
| 226 | } |
| 227 | } |
| 228 | |
| 229 | int64_t inOffset = rowIdx * inColsPerRow + colIdx; |
| 230 | PackedVec in_vec = reinterpret_cast<PackedVec const*>(in)[inOffset]; |
| 231 | PackedVec quant_input; |
| 232 | if constexpr (FUSE_SILU_MUL) { |
| 233 | PackedVec in_vec_up = |
| 234 | reinterpret_cast<PackedVec const*>(in)[inOffset + colsPerRow]; |
| 235 | quant_input = compute_silu_mul(in_vec, in_vec_up); |
| 236 | } else { |
| 237 | quant_input = in_vec; |
| 238 | } |
| 239 | |
| 240 | int64_t outOffset = rowIdx * colsPerRow + colIdx; |
| 241 | auto& out_pos = out[outOffset]; |
| 242 | |
| 243 | // MXFP4 has no global scale - only block-level E8M0 scale factors |
| 244 | constexpr float SFScaleVal = 1.0f; |
| 245 | |
| 246 | uint32_t* SFout_in_expert = |
| 247 | SFout + output_scale_offset_by_experts[expert_idx] * numKTiles; |
| 248 | |
| 249 | auto sf_out = |
| 250 | cvt_quant_to_fp4_get_sf_out_offset<uint32_t, MXFP4_NUM_THREADS_PER_SF>( |
| 251 | rowIdx_in_expert, colIdx, numKTiles, SFout_in_expert); |
| 252 | |
| 253 | out_pos = |
| 254 | cvt_warp_fp16_to_fp4<Type, MXFP4_NUM_THREADS_PER_SF, /*UE8M0_SF=*/true>( |
| 255 | quant_input, SFScaleVal, sf_out); |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | template <typename T, bool FUSE_SILU_MUL = false> |
| 260 | void mxfp4_quant_impl(void* output, void* output_scale, void* input, |
| 261 | void* input_offset_by_experts, |
| 262 | void* output_scale_offset_by_experts, int m_topk, int k, |
| 263 | int n_experts, cudaStream_t stream) { |
| 264 | int multiProcessorCount = |
| 265 | get_device_attribute(cudaDevAttrMultiProcessorCount, -1); |
| 266 | |
| 267 | int const workSizePerRow = k / ELTS_PER_THREAD; |
| 268 | int const totalWorkSize = m_topk * workSizePerRow; |
| 269 | dim3 block(std::min(workSizePerRow, 512)); |
| 270 | int const numBlocksPerSM = |
| 271 | vllm_runtime_blocks_per_sm(static_cast<int>(block.x)); |
| 272 | dim3 grid(std::min(static_cast<int>((totalWorkSize + block.x - 1) / block.x), |
| 273 | multiProcessorCount * numBlocksPerSM)); |
| 274 | while (grid.x <= multiProcessorCount && block.x > 64) { |
| 275 | grid.x *= 2; |
| 276 | block.x = (block.x + 1) / 2; |
| 277 | } |
| 278 | |
| 279 | int const blockRepeat = |
| 280 | (totalWorkSize + block.x * grid.x - 1) / (block.x * grid.x); |
| 281 | if (blockRepeat > 1) { |
| 282 | size_t shared_mem_size = (n_experts + 1) * sizeof(uint32_t); |
| 283 | if (n_experts >= 4) { |
| 284 | mxfp4_cvt_fp16_to_fp4<T, FUSE_SILU_MUL, false> |
| 285 | <<<grid, block, shared_mem_size, stream>>>( |
| 286 | m_topk, k, reinterpret_cast<T*>(input), |
| 287 | reinterpret_cast<fp4_packed_t*>(output), |
| 288 | reinterpret_cast<uint32_t*>(output_scale), |
| 289 | reinterpret_cast<uint32_t*>(input_offset_by_experts), |
| 290 | reinterpret_cast<uint32_t*>(output_scale_offset_by_experts), |
| 291 | n_experts); |
| 292 | } else { |
| 293 | mxfp4_cvt_fp16_to_fp4<T, FUSE_SILU_MUL, true> |
| 294 | <<<grid, block, shared_mem_size, stream>>>( |
| 295 | m_topk, k, reinterpret_cast<T*>(input), |
| 296 | reinterpret_cast<fp4_packed_t*>(output), |
| 297 | reinterpret_cast<uint32_t*>(output_scale), |
| 298 | reinterpret_cast<uint32_t*>(input_offset_by_experts), |
| 299 | reinterpret_cast<uint32_t*>(output_scale_offset_by_experts), |
| 300 | n_experts); |
| 301 | } |
| 302 | } else { |
| 303 | if (n_experts >= 16) { |
| 304 | mxfp4_cvt_fp16_to_fp4<T, FUSE_SILU_MUL, false> |
| 305 | <<<grid, block, 0, stream>>>( |
| 306 | m_topk, k, reinterpret_cast<T*>(input), |
| 307 | reinterpret_cast<fp4_packed_t*>(output), |
| 308 | reinterpret_cast<uint32_t*>(output_scale), |
| 309 | reinterpret_cast<uint32_t*>(input_offset_by_experts), |
| 310 | reinterpret_cast<uint32_t*>(output_scale_offset_by_experts), |
| 311 | n_experts, /* bool low_latency */ true); |
| 312 | } else { |
| 313 | mxfp4_cvt_fp16_to_fp4<T, FUSE_SILU_MUL, true><<<grid, block, 0, stream>>>( |
| 314 | m_topk, k, reinterpret_cast<T*>(input), |
| 315 | reinterpret_cast<fp4_packed_t*>(output), |
| 316 | reinterpret_cast<uint32_t*>(output_scale), |
| 317 | reinterpret_cast<uint32_t*>(input_offset_by_experts), |
| 318 | reinterpret_cast<uint32_t*>(output_scale_offset_by_experts), |
| 319 | n_experts, /* bool low_latency */ true); |
| 320 | } |
| 321 | } |
| 322 | } |
| 323 | |
| 324 | } // namespace vllm |
| 325 | |
| 326 | /*Quantization entry for mxfp4 experts quantization*/ |
| 327 | #define CHECK_TH_CUDA(x, m) \ |
| 328 | STD_TORCH_CHECK(x.is_cuda(), m, "must be a CUDA tensor") |
| 329 | #define CHECK_CONTIGUOUS(x, m) \ |
| 330 | STD_TORCH_CHECK(x.is_contiguous(), m, "must be contiguous") |
| 331 | #define CHECK_INPUT(x, m) \ |
| 332 | CHECK_TH_CUDA(x, m); \ |
| 333 | CHECK_CONTIGUOUS(x, m); |
| 334 | |
| 335 | constexpr auto HALF = torch::headeronly::ScalarType::Half; |
| 336 | constexpr auto BF16 = torch::headeronly::ScalarType::BFloat16; |
| 337 | constexpr auto INT = torch::headeronly::ScalarType::Int; |
| 338 | constexpr auto UINT8 = torch::headeronly::ScalarType::Byte; |
| 339 | |
| 340 | static constexpr int MXFP4_BLOCK_SIZE = 32; |
| 341 | |
| 342 | static void validate_mxfp4_experts_quant_inputs( |
| 343 | torch::stable::Tensor const& output, |
| 344 | torch::stable::Tensor const& output_scale, |
| 345 | torch::stable::Tensor const& input, |
| 346 | torch::stable::Tensor const& input_offset_by_experts, |
| 347 | torch::stable::Tensor const& output_scale_offset_by_experts, |
| 348 | int64_t n_experts, int64_t m_topk, int64_t k) { |
| 349 | CHECK_INPUT(output, "output"); |
| 350 | CHECK_INPUT(output_scale, "output_scale"); |
| 351 | CHECK_INPUT(input, "input"); |
| 352 | CHECK_INPUT(input_offset_by_experts, "input_offset_by_experts"); |
| 353 | CHECK_INPUT(output_scale_offset_by_experts, "output_scale_offset_by_experts"); |
| 354 | |
| 355 | STD_TORCH_CHECK(output.dim() == 2); |
| 356 | STD_TORCH_CHECK(output_scale.dim() == 2); |
| 357 | STD_TORCH_CHECK(input.dim() == 2); |
| 358 | STD_TORCH_CHECK(input_offset_by_experts.dim() == 1); |
| 359 | STD_TORCH_CHECK(output_scale_offset_by_experts.dim() == 1); |
| 360 | |
| 361 | STD_TORCH_CHECK(input.scalar_type() == HALF || input.scalar_type() == BF16); |
| 362 | STD_TORCH_CHECK(input_offset_by_experts.scalar_type() == INT); |
| 363 | STD_TORCH_CHECK(output_scale_offset_by_experts.scalar_type() == INT); |
| 364 | // output is uint8 (two mxfp4 values packed into one uint8) |
| 365 | // output_scale is int32 (four E8M0 values packed into one int32) |
| 366 | STD_TORCH_CHECK(output.scalar_type() == UINT8); |
| 367 | STD_TORCH_CHECK(output_scale.scalar_type() == INT); |
| 368 | |
| 369 | STD_TORCH_CHECK(k % MXFP4_BLOCK_SIZE == 0, "k must be a multiple of 32"); |
| 370 | STD_TORCH_CHECK(input_offset_by_experts.size(0) == n_experts + 1); |
| 371 | STD_TORCH_CHECK(output_scale_offset_by_experts.size(0) == n_experts + 1); |
| 372 | STD_TORCH_CHECK(output.size(0) == m_topk); |
| 373 | STD_TORCH_CHECK(output.size(1) == k / 2); |
| 374 | int scales_k = k / MXFP4_BLOCK_SIZE; |
| 375 | // K-dimension scale columns padded to a multiple of 4 for swizzle layout |
| 376 | int padded_k = (scales_k + (4 - 1)) / 4 * 4; |
| 377 | // 4 = 4 E8M0 values packed into one int32 |
| 378 | STD_TORCH_CHECK(output_scale.size(1) * 4 == padded_k); |
| 379 | } |
| 380 | |
| 381 | #endif // VLLM_MXFP4_EXPERTS_QUANT_SUPPORTED |
| 382 | |
| 383 | static bool mxfp4_experts_quant_sm_supported(int64_t cuda_device_capability) { |
| 384 | #if VLLM_MXFP4_EXPERTS_QUANT_SUPPORTED |
| 385 | return cuda_device_capability >= 100 && cuda_device_capability < 120; |
| 386 | #else |
| 387 | return false; |
| 388 | #endif |
| 389 | } |
| 390 | |
| 391 | void mxfp4_experts_quant( |
| 392 | torch::stable::Tensor& output, torch::stable::Tensor& output_scale, |
| 393 | torch::stable::Tensor const& input, |
| 394 | torch::stable::Tensor const& input_offset_by_experts, |
| 395 | torch::stable::Tensor const& output_scale_offset_by_experts, |
| 396 | int64_t n_experts) { |
| 397 | #if VLLM_MXFP4_EXPERTS_QUANT_SUPPORTED |
| 398 | int32_t sm = get_sm_version_num(); |
| 399 | STD_TORCH_CHECK(mxfp4_experts_quant_sm_supported(sm), |
| 400 | "No compiled MXFP4 experts quant kernel for SM ", sm, |
| 401 | ". Recompile with SM10x/11x FP4 support and CUDA >= 12.9."); |
| 402 | |
| 403 | auto m_topk = input.size(0); |
| 404 | auto k = input.size(1); |
| 405 | |
| 406 | validate_mxfp4_experts_quant_inputs( |
| 407 | output, output_scale, input, input_offset_by_experts, |
| 408 | output_scale_offset_by_experts, n_experts, m_topk, k); |
| 409 | |
| 410 | const torch::stable::accelerator::DeviceGuard device_guard( |
| 411 | input.get_device_index()); |
| 412 | const cudaStream_t stream = get_current_cuda_stream(input.get_device_index()); |
| 413 | |
| 414 | VLLM_STABLE_DISPATCH_HALF_TYPES( |
| 415 | input.scalar_type(), "mxfp4_experts_quant_kernel", [&] { |
| 416 | using cuda_type = vllm::CUDATypeConverter<scalar_t>::Type; |
| 417 | vllm::mxfp4_quant_impl<cuda_type, /*FUSE_SILU_MUL=*/false>( |
| 418 | output.data_ptr(), output_scale.data_ptr(), input.data_ptr(), |
| 419 | input_offset_by_experts.data_ptr(), |
| 420 | output_scale_offset_by_experts.data_ptr(), m_topk, k, n_experts, |
| 421 | stream); |
| 422 | }); |
| 423 | #else |
| 424 | STD_TORCH_CHECK_NOT_IMPLEMENTED(false, |
| 425 | "MXFP4 experts quant requires CUDA >= 12.9."); |
| 426 | #endif |
| 427 | } |
| 428 | |
| 429 | void silu_and_mul_mxfp4_experts_quant( |
| 430 | torch::stable::Tensor& output, torch::stable::Tensor& output_scale, |
| 431 | torch::stable::Tensor const& input, |
| 432 | torch::stable::Tensor const& input_offset_by_experts, |
| 433 | torch::stable::Tensor const& output_scale_offset_by_experts, |
| 434 | int64_t n_experts) { |
| 435 | #if VLLM_MXFP4_EXPERTS_QUANT_SUPPORTED |
| 436 | int32_t sm = get_sm_version_num(); |
| 437 | STD_TORCH_CHECK(mxfp4_experts_quant_sm_supported(sm), |
| 438 | "No compiled SiLU+Mul MXFP4 experts quant kernel for SM ", sm, |
| 439 | ". Recompile with SM10x/11x FP4 support and CUDA >= 12.9."); |
| 440 | |
| 441 | auto m_topk = input.size(0); |
| 442 | auto k_times_2 = input.size(1); |
| 443 | STD_TORCH_CHECK(k_times_2 % 2 == 0, "input width must be even (gate || up)"); |
| 444 | auto k = k_times_2 / 2; |
| 445 | |
| 446 | validate_mxfp4_experts_quant_inputs( |
| 447 | output, output_scale, input, input_offset_by_experts, |
| 448 | output_scale_offset_by_experts, n_experts, m_topk, k); |
| 449 | |
| 450 | const torch::stable::accelerator::DeviceGuard device_guard( |
| 451 | input.get_device_index()); |
| 452 | const cudaStream_t stream = get_current_cuda_stream(input.get_device_index()); |
| 453 | |
| 454 | VLLM_STABLE_DISPATCH_HALF_TYPES( |
| 455 | input.scalar_type(), "silu_mul_mxfp4_experts_quant_kernel", [&] { |
| 456 | using cuda_type = vllm::CUDATypeConverter<scalar_t>::Type; |
| 457 | vllm::mxfp4_quant_impl<cuda_type, /*FUSE_SILU_MUL=*/true>( |
| 458 | output.data_ptr(), output_scale.data_ptr(), input.data_ptr(), |
| 459 | input_offset_by_experts.data_ptr(), |
| 460 | output_scale_offset_by_experts.data_ptr(), m_topk, k, n_experts, |
| 461 | stream); |
| 462 | }); |
| 463 | #else |
| 464 | STD_TORCH_CHECK_NOT_IMPLEMENTED( |
| 465 | false, "SiLU+Mul MXFP4 experts quant requires CUDA >= 12.9."); |
| 466 | #endif |
| 467 | } |
| 468 | |
| 469 | bool mxfp4_experts_quant_supported(int64_t cuda_device_capability) { |
| 470 | return mxfp4_experts_quant_sm_supported(cuda_device_capability); |
| 471 | } |
| 472 | |
| 473 | STABLE_TORCH_LIBRARY_FRAGMENT(_C, m) { |
| 474 | m.def("mxfp4_experts_quant_supported(int cuda_device_capability) -> bool"); |
| 475 | } |
| 476 | |
| 477 | // Registered here so the CUDA 12.8 stub and CUDA 12.9+ implementation stay |
| 478 | // tied to the same translation unit. |
| 479 | STABLE_TORCH_LIBRARY_IMPL(_C, CUDA, m) { |
| 480 | m.impl("mxfp4_experts_quant", TORCH_BOX(&mxfp4_experts_quant)); |
| 481 | m.impl("silu_and_mul_mxfp4_experts_quant", |
| 482 | TORCH_BOX(&silu_and_mul_mxfp4_experts_quant)); |
| 483 | } |
| 484 | |
| 485 | STABLE_TORCH_LIBRARY_IMPL(_C, CompositeExplicitAutograd, m) { |
| 486 | m.impl("mxfp4_experts_quant_supported", |
| 487 | TORCH_BOX(&mxfp4_experts_quant_supported)); |
| 488 | } |