| 1 | #include "marlin.cuh" |
| 2 | |
| 3 | #include <torch/csrc/stable/accelerator.h> |
| 4 | #include <torch/csrc/stable/library.h> |
| 5 | #include <torch/csrc/stable/ops.h> |
| 6 | #include <torch/csrc/stable/tensor.h> |
| 7 | #include <torch/headeronly/core/ScalarType.h> |
| 8 | #include <torch/headeronly/util/Exception.h> |
| 9 | |
| 10 | #include "libtorch_stable/torch_utils.h" |
| 11 | |
| 12 | namespace marlin { |
| 13 | |
| 14 | template <int const num_threads, int const num_bits, bool is_a_8bit> |
| 15 | __global__ void gptq_marlin_repack_kernel( |
| 16 | uint32_t const* __restrict__ b_q_weight_ptr, uint32_t* __restrict__ out_ptr, |
| 17 | int size_k, int size_n) { |
| 18 | constexpr int pack_factor = 32 / num_bits; |
| 19 | |
| 20 | constexpr int target_tile_n_size = tile_n_size / (is_a_8bit ? 2 : 1); |
| 21 | constexpr int target_tile_k_size = tile_k_size * (is_a_8bit ? 2 : 1); |
| 22 | int k_tiles = size_k / target_tile_k_size; |
| 23 | int n_tiles = size_n / target_tile_n_size; |
| 24 | int block_k_tiles = div_ceil(k_tiles, gridDim.x); |
| 25 | |
| 26 | auto start_k_tile = blockIdx.x * block_k_tiles; |
| 27 | if (start_k_tile >= k_tiles) { |
| 28 | return; |
| 29 | } |
| 30 | |
| 31 | int finish_k_tile = min(start_k_tile + block_k_tiles, k_tiles); |
| 32 | |
| 33 | // Wait until the next thread tile has been loaded to shared memory. |
| 34 | auto wait_for_stage = [&]() { |
| 35 | // We only have `stages - 2` active fetches since we are double buffering |
| 36 | // and can only issue the next fetch when it is guaranteed that the previous |
| 37 | // shared memory load is fully complete (as it may otherwise be |
| 38 | // overwritten). |
| 39 | cp_async_wait<repack_stages - 2>(); |
| 40 | __syncthreads(); |
| 41 | }; |
| 42 | |
| 43 | extern __shared__ int4 sh[]; |
| 44 | |
| 45 | int4* sh_pipe_ptr = sh; |
| 46 | |
| 47 | constexpr int tile_ints = target_tile_k_size / pack_factor; |
| 48 | |
| 49 | constexpr int stage_n_threads = target_tile_n_size / 4; |
| 50 | constexpr int stage_k_threads = tile_ints; |
| 51 | constexpr int stage_size = stage_k_threads * stage_n_threads; |
| 52 | |
| 53 | auto fetch_to_shared = [&](int pipe, int k_tile_id, int n_tile_id) { |
| 54 | if (n_tile_id >= n_tiles) { |
| 55 | cp_async_fence(); |
| 56 | return; |
| 57 | } |
| 58 | |
| 59 | int first_n = n_tile_id * target_tile_n_size; |
| 60 | |
| 61 | int4* sh_ptr = sh_pipe_ptr + stage_size * pipe; |
| 62 | |
| 63 | if (threadIdx.x < stage_size) { |
| 64 | auto k_id = threadIdx.x / stage_n_threads; |
| 65 | auto n_id = threadIdx.x % stage_n_threads; |
| 66 | |
| 67 | int first_k = k_tile_id * target_tile_k_size; |
| 68 | int first_k_packed = first_k / pack_factor; |
| 69 | |
| 70 | cp_async4(&sh_ptr[k_id * stage_n_threads + n_id], |
| 71 | reinterpret_cast<int4 const*>( |
| 72 | &(b_q_weight_ptr[(first_k_packed + k_id) * size_n + |
| 73 | first_n + (n_id * 4)]))); |
| 74 | } |
| 75 | |
| 76 | cp_async_fence(); |
| 77 | }; |
| 78 | |
| 79 | auto repack_tile = [&](int pipe, int k_tile_id, int n_tile_id) { |
| 80 | if (n_tile_id >= n_tiles) { |
| 81 | return; |
| 82 | } |
| 83 | |
| 84 | auto warp_id = threadIdx.x / 32; |
| 85 | auto th_id = threadIdx.x % 32; |
| 86 | |
| 87 | if (warp_id >= 4) { |
| 88 | return; |
| 89 | } |
| 90 | |
| 91 | int tc_col = th_id / 4; |
| 92 | int tc_row = (th_id % 4) * (is_a_8bit ? 4 : 2); |
| 93 | |
| 94 | constexpr int tc_offsets[4] = {0, 1, 8, 9}; |
| 95 | |
| 96 | int cur_n = (warp_id / (is_a_8bit ? 2 : 1)) * 16 + tc_col; |
| 97 | |
| 98 | constexpr int sh_stride = target_tile_n_size; |
| 99 | constexpr uint32_t mask = (1 << num_bits) - 1; |
| 100 | |
| 101 | int4* sh_stage_ptr = sh_pipe_ptr + stage_size * pipe; |
| 102 | uint32_t* sh_stage_int_ptr = reinterpret_cast<uint32_t*>(sh_stage_ptr); |
| 103 | |
| 104 | uint32_t vals[8]; |
| 105 | |
| 106 | uint32_t b1_vals[tile_ints]; |
| 107 | uint32_t b2_vals[tile_ints]; |
| 108 | |
| 109 | #pragma unroll |
| 110 | for (int i = 0; i < tile_ints; i++) { |
| 111 | if constexpr (is_a_8bit) { |
| 112 | b1_vals[i] = |
| 113 | sh_stage_int_ptr[cur_n + sh_stride * i + (warp_id % 2) * 8]; |
| 114 | } else { |
| 115 | b1_vals[i] = sh_stage_int_ptr[cur_n + sh_stride * i]; |
| 116 | b2_vals[i] = sh_stage_int_ptr[cur_n + 8 + sh_stride * i]; |
| 117 | } |
| 118 | } |
| 119 | |
| 120 | #pragma unroll |
| 121 | for (int i = 0; i < 4; i++) { |
| 122 | int cur_elem = tc_row + (is_a_8bit ? i : tc_offsets[i]); |
| 123 | int cur_int = cur_elem / pack_factor; |
| 124 | int cur_pos = cur_elem % pack_factor; |
| 125 | |
| 126 | vals[i] = (b1_vals[cur_int] >> (cur_pos * num_bits)) & mask; |
| 127 | if constexpr (is_a_8bit) |
| 128 | vals[4 + i] = |
| 129 | (b1_vals[cur_int + tile_ints / 2] >> (cur_pos * num_bits)) & mask; |
| 130 | else |
| 131 | vals[4 + i] = (b2_vals[cur_int] >> (cur_pos * num_bits)) & mask; |
| 132 | } |
| 133 | |
| 134 | constexpr int tile_size = |
| 135 | target_tile_k_size * target_tile_n_size / pack_factor; |
| 136 | int out_offset = (k_tile_id * n_tiles + n_tile_id) * tile_size; |
| 137 | |
| 138 | // Result of: |
| 139 | // https://github.com/NVIDIA/FasterTransformer/blob/main/src/fastertransformer/cutlass_extensions/include/cutlass_extensions/interleaved_numeric_conversion.h |
| 140 | if constexpr (!is_a_8bit && num_bits == 4) { |
| 141 | int pack_idx[8] = {0, 2, 4, 6, 1, 3, 5, 7}; |
| 142 | |
| 143 | uint32_t res = 0; |
| 144 | #pragma unroll |
| 145 | for (int i = 0; i < 8; i++) { |
| 146 | res |= vals[pack_idx[i]] << (i * 4); |
| 147 | } |
| 148 | |
| 149 | out_ptr[out_offset + th_id * 4 + warp_id] = res; |
| 150 | |
| 151 | } else if constexpr (is_a_8bit && num_bits == 4) { |
| 152 | int pack_idx[8] = {0, 4, 1, 5, 2, 6, 3, 7}; |
| 153 | |
| 154 | uint32_t res = 0; |
| 155 | #pragma unroll |
| 156 | for (int i = 0; i < 8; i++) { |
| 157 | res |= vals[pack_idx[i]] << (i * 4); |
| 158 | } |
| 159 | |
| 160 | out_ptr[out_offset + th_id * 4 + warp_id] = res; |
| 161 | |
| 162 | } else { |
| 163 | constexpr int pack_idx[4] = {0, 2, 1, 3}; |
| 164 | |
| 165 | uint32_t res1 = 0; |
| 166 | uint32_t res2 = 0; |
| 167 | #pragma unroll |
| 168 | for (int i = 0; i < 4; i++) { |
| 169 | const int ii = is_a_8bit ? i : pack_idx[i]; |
| 170 | res1 |= vals[ii] << (i * 8); |
| 171 | res2 |= vals[4 + ii] << (i * 8); |
| 172 | } |
| 173 | |
| 174 | out_ptr[out_offset + th_id * 8 + (warp_id * 2) + 0] = res1; |
| 175 | out_ptr[out_offset + th_id * 8 + (warp_id * 2) + 1] = res2; |
| 176 | } |
| 177 | }; |
| 178 | |
| 179 | auto start_pipes = [&](int k_tile_id, int n_tile_id) { |
| 180 | #pragma unroll |
| 181 | for (int pipe = 0; pipe < repack_stages - 1; pipe++) { |
| 182 | fetch_to_shared(pipe, k_tile_id, n_tile_id + pipe); |
| 183 | } |
| 184 | |
| 185 | wait_for_stage(); |
| 186 | }; |
| 187 | #pragma unroll |
| 188 | for (int k_tile_id = start_k_tile; k_tile_id < finish_k_tile; k_tile_id++) { |
| 189 | int n_tile_id = 0; |
| 190 | |
| 191 | start_pipes(k_tile_id, n_tile_id); |
| 192 | |
| 193 | while (n_tile_id < n_tiles) { |
| 194 | #pragma unroll |
| 195 | for (int pipe = 0; pipe < repack_stages; pipe++) { |
| 196 | fetch_to_shared((pipe + repack_stages - 1) % repack_stages, k_tile_id, |
| 197 | n_tile_id + pipe + repack_stages - 1); |
| 198 | repack_tile(pipe, k_tile_id, n_tile_id + pipe); |
| 199 | wait_for_stage(); |
| 200 | } |
| 201 | n_tile_id += repack_stages; |
| 202 | } |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | } // namespace marlin |
| 207 | |
| 208 | #define CALL_IF(NUM_BITS, IS_A_8BIT) \ |
| 209 | else if (num_bits == NUM_BITS && is_a_8bit == IS_A_8BIT) { \ |
| 210 | cudaFuncSetAttribute( \ |
| 211 | marlin::gptq_marlin_repack_kernel<marlin::repack_threads, NUM_BITS, \ |
| 212 | IS_A_8BIT>, \ |
| 213 | cudaFuncAttributeMaxDynamicSharedMemorySize, max_shared_mem); \ |
| 214 | marlin::gptq_marlin_repack_kernel<marlin::repack_threads, NUM_BITS, \ |
| 215 | IS_A_8BIT> \ |
| 216 | <<<blocks, marlin::repack_threads, max_shared_mem, stream>>>( \ |
| 217 | b_q_weight_ptr, out_ptr, size_k, size_n); \ |
| 218 | } |
| 219 | |
| 220 | torch::stable::Tensor gptq_marlin_repack(torch::stable::Tensor& b_q_weight, |
| 221 | int64_t size_k, int64_t size_n, |
| 222 | int64_t num_bits, bool is_a_8bit) { |
| 223 | // Verify compatibility with marlin tile of 16x64 |
| 224 | STD_TORCH_CHECK(size_k % marlin::tile_k_size == 0, "size_k = ", size_k, |
| 225 | " is not divisible by tile_k_size = ", marlin::tile_k_size); |
| 226 | STD_TORCH_CHECK(size_n % marlin::tile_n_size == 0, "size_n = ", size_n, |
| 227 | " is not divisible by tile_n_size = ", marlin::tile_n_size); |
| 228 | |
| 229 | STD_TORCH_CHECK(num_bits == 4 || num_bits == 8, |
| 230 | "num_bits must be 4 or 8. Got = ", num_bits); |
| 231 | int const pack_factor = 32 / num_bits; |
| 232 | |
| 233 | // Verify B |
| 234 | STD_TORCH_CHECK((size_k / pack_factor) == b_q_weight.size(0), |
| 235 | "Shape mismatch: b_q_weight.size(0) = ", b_q_weight.size(0), |
| 236 | ", size_k = ", size_k, ", pack_factor = ", pack_factor); |
| 237 | STD_TORCH_CHECK(b_q_weight.size(1) == size_n, |
| 238 | "b_q_weight.size(1) = ", b_q_weight.size(1), |
| 239 | " is not size_n = ", size_n); |
| 240 | |
| 241 | // Verify device and strides |
| 242 | STD_TORCH_CHECK(b_q_weight.is_cuda(), "b_q_weight is not on GPU"); |
| 243 | STD_TORCH_CHECK(b_q_weight.is_contiguous(), "b_q_weight is not contiguous"); |
| 244 | STD_TORCH_CHECK( |
| 245 | b_q_weight.scalar_type() == torch::headeronly::ScalarType::Int, |
| 246 | "b_q_weight type is not kInt"); |
| 247 | |
| 248 | const int32_t device_index = b_q_weight.get_device_index(); |
| 249 | torch::stable::accelerator::DeviceGuard device_guard(device_index); |
| 250 | const cudaStream_t stream = get_current_cuda_stream(device_index); |
| 251 | |
| 252 | // Alloc buffers |
| 253 | torch::stable::Tensor out = torch::stable::empty( |
| 254 | {size_k / marlin::tile_size, size_n * marlin::tile_size / pack_factor}, |
| 255 | b_q_weight.scalar_type(), std::nullopt, b_q_weight.device()); |
| 256 | |
| 257 | // Get ptrs |
| 258 | uint32_t const* b_q_weight_ptr = |
| 259 | reinterpret_cast<uint32_t const*>(b_q_weight.const_data_ptr()); |
| 260 | uint32_t* out_ptr = reinterpret_cast<uint32_t*>(out.mutable_data_ptr()); |
| 261 | |
| 262 | int blocks; |
| 263 | cudaDeviceGetAttribute(&blocks, cudaDevAttrMultiProcessorCount, device_index); |
| 264 | |
| 265 | int max_shared_mem = 0; |
| 266 | cudaDeviceGetAttribute(&max_shared_mem, |
| 267 | cudaDevAttrMaxSharedMemoryPerBlockOptin, device_index); |
| 268 | STD_TORCH_CHECK(max_shared_mem > 0); |
| 269 | |
| 270 | if (false) { |
| 271 | } |
| 272 | CALL_IF(4, false) |
| 273 | CALL_IF(8, false) |
| 274 | |
| 275 | CALL_IF(4, true) |
| 276 | CALL_IF(8, true) |
| 277 | |
| 278 | else { |
| 279 | STD_TORCH_CHECK(false, "Unsupported repack config: num_bits = ", num_bits, |
| 280 | ", is_a_8bit = ", is_a_8bit); |
| 281 | } |
| 282 | |
| 283 | return out; |
| 284 | } |
| 285 | |
| 286 | STABLE_TORCH_LIBRARY_IMPL(_C, CUDA, m) { |
| 287 | m.impl("gptq_marlin_repack", TORCH_BOX(&gptq_marlin_repack)); |
| 288 | } |