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1 # SPDX-License-Identifier: Apache-2.0
2 # SPDX-FileCopyrightText: Copyright contributors to the vLLM project
3 """HY V4 (``hy_v4``) model — hardware-isolated entry point.
4
5 HY V4 combines three architectural pieces:
6
7 - **iHC** (independent Hyper-Connections): the single residual stream is
8 replaced by ``hc_mult`` parallel residual channels, gated per sub-block.
9 - **MLA + lightning indexer**: multi-head latent attention with an optional
10 DSA-style sparse top-k selection, plus an output gate and a learnable sink.
11 - **MoE**: sigmoid-routed experts with a clamped SwiGLU and shared experts.
12
13 The package is organized like `vllm.models.deepseek_v32`: this module is the
14 only public entry point and dispatches on the current platform, so registry
15 entries never reach into a platform subpackage.
16
17 NVIDIA and ROCm are supported, the latter through `amd/`. The port also drops
18 the reference implementation's HPC/TPCP fusion paths, which depend on
19 infrastructure that does not exist in this tree.
20 """
21
22 from typing import TYPE_CHECKING
23
24 from vllm.platforms import current_platform
25
26 if current_platform.is_xpu():
27 raise NotImplementedError("hy_v4 does not yet support XPU.")
28
29 # The NVIDIA branch is the static default that type-checkers see; the ROCm
30 # branch overrides it at runtime (kept type-compatible via type: ignore).
31 if TYPE_CHECKING or not current_platform.is_rocm():
32 from .nvidia.model import HYV4ForCausalLM
33 else:
34 from .amd.model import HYV4ForCausalLM # type: ignore[assignment]
35
36 # The draft head has no ROCm-specific implementation yet.
37 from .nvidia.mtp import HYV4MTP # noqa: E402
38
39 __all__ = [
40 "HYV4ForCausalLM",
41 "HYV4MTP",
42 ]