disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress

Richard Henderson committed about 1 month ago

disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands

Richard Henderson committed about 1 month ago

disas/riscv: Tidy dec initialization in disasm_inst

Richard Henderson committed about 1 month ago

disas/riscv: Reduce rv_insn to uint32_t

Richard Henderson committed about 1 month ago

disas/riscv: Move operand extractors earlier in file

Richard Henderson committed about 1 month ago

target/riscv: allow menvcfg/henvcfg LPE and SSE bits on RV32

A-Shehab committed about 2 months ago

hw/riscv/riscv-iommu: preserve requested perm in spa_fetch()

Andrew Jones committed 2 months ago

hw/riscv/riscv-iommu: fix U-bit check to apply only to leaf S/VS-stage PTEs

Andrew Jones committed 2 months ago

disas/riscv: Use extract helpers for operand fields

TANG Tiancheng committed 3 months ago

disas/riscv: Decode unsigned vector immediates as unsigned

TANG Tiancheng committed 3 months ago

disas/riscv: Use signed type for vector immediates

TANG Tiancheng committed 3 months ago

disas/riscv: Fix 6-bit immediate extraction

TANG Tiancheng committed 3 months ago

disas/riscv: Fix th.srri decoding

TANG Tiancheng committed 3 months ago

tests/qtest: Add seed CSR zero extension test

Ivan Efremov committed about 2 months ago

target/riscv: Fix seed CSR sign extension

Ivan Efremov committed about 2 months ago

target/riscv: do not count ECALL in minstret

Zephyr Li committed about 2 months ago

tests/tcg/riscv64: Add test for Zicclsm

Frank Chang committed about 1 month ago

target/riscv: Expose Zicclsm as a CPU property and update RVA22U64 profile

Frank Chang committed about 1 month ago

target/riscv: Support raising misaligned exceptions for vector loads/stores

Frank Chang committed about 1 month ago

target/riscv: Support raising misaligned exceptions for floating-point loads/stores

Frank Chang committed about 1 month ago