hw/ufs: Add a generic SysBus frontend

Jeuk Kim committed about 2 months ago

hw/ufs: Separate the controller core from the PCI frontend

Jeuk Kim committed about 2 months ago

target/riscv/tcg: sret in virtual user mode raises virtual instruction exception

Christian S. Lima committed about 2 months ago

target/riscv: Make Zcmt JVT loads endian-aware

Xu Liu committed about 1 month ago

tests/tcg/riscv64: add misa write test

Vladimir Isaev committed about 1 month ago

riscv: csr: do not drop C bit on misa write

Vladimir Isaev committed about 1 month ago

target/riscv: Allow UXL to be 3 in mstatus on rv128

Frédéric Pétrot committed about 1 month ago

target/riscv: Fix sstatus update in rv128

Frédéric Pétrot committed about 1 month ago

target/riscv: Restore register dump zero padding

Joel Stanley committed about 1 month ago

tests/qtest: remove trace output from k230 watchdog test

Chao Liu committed about 1 month ago

target/riscv: enforce even register constraints for Zdinx fcvt pairs

wangyang committed about 1 month ago

target/riscv: reject FMV.X.W/FMV.W.X under Zfinx

wangyang committed about 1 month ago

target/riscv: honor zicbo* envcfg gating in linux-user mode

wangyang committed about 1 month ago

disas/riscv: Sort riscv-op.c.inc

Richard Henderson committed about 1 month ago

disas/riscv: Split rvi_opcode_data

Richard Henderson committed about 1 month ago

disas/riscv: Tidy decode of mop.r.n and mop.rr.n

Richard Henderson committed about 1 month ago

disas/riscv: Tidy decode of c.mop.n

Richard Henderson committed about 1 month ago

disas/riscv: Merge all c.mop.n to one pattern

Richard Henderson committed about 1 month ago

disas/riscv: Merge all mop.rr.n to one pattern

Richard Henderson committed about 1 month ago

disas/riscv: Merge all mop.r.n to one pattern

Richard Henderson committed about 1 month ago