@samitouri / QOSamiQemu

Official QOSAMI-QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are disabled. Please only use release tarballs from the QEMU website.

Code Commits 132,582 Issues Pulls Sessions CI/CD
master
master

target/arm: GICv5 cpuif: Implement PPI enable register

Peter Maydell committed 6 months ago

2f36257492

target/arm: GICv5 cpuif: Implement PPI pending status registers

Peter Maydell committed 6 months ago

585dad9e79

target/arm: GICv5 cpuif: Implement PPI handling mode register

Peter Maydell committed 6 months ago

394ad2e928

target/arm: GICv5 cpuif: Implement GICv5 PPI active set/clear registers

Peter Maydell committed 6 months ago

4ea9fa2637

target/arm: GICv5 cpuif: Implement ICC_IDR0_EL1

Peter Maydell committed 6 months ago

7c05b9ef75

target/arm: GICv5 cpuif: Implement ICC_IAFFIDR_EL1

Peter Maydell committed 6 months ago

829ce41fbe

hw/intc/arm_gicv5: Cache pending LPIs in a hash table

Peter Maydell committed 6 months ago

b791d607c3

hw/intc/arm_gicv5: Implement CoreSight ID registers

Peter Maydell committed 6 months ago

22232793ec

hw/intc/arm_gicv5: Implement IRS_PE_{CR0, SELR, STATUSR}

Peter Maydell committed 6 months ago

ce71478e81

hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR

Peter Maydell committed 6 months ago

d304e788c6

hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1

Peter Maydell committed 6 months ago

75ded6e07a

hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events

Peter Maydell committed 6 months ago

33185e1d64

hw/intc/arm_gicv5: Implement IRS_SPI_{SELR, STATUSR, CFGR, DOMAINR}

Peter Maydell committed 6 months ago

19fd9cd10b

target/arm: GICv5 cpuif: Implement GIC CDRCFG and ICC_ICSR_EL1

Peter Maydell committed 6 months ago

127a41fc00

hw/intc/arm_gicv5: Implement gicv5_request_config()

Peter Maydell committed 6 months ago

a05e512406

hw/intc/arm_gicv5: Make gicv5_set_* update SPI state

Peter Maydell committed 6 months ago

5beb48ab53

hw/intc/arm_gicv5: Create backing state for SPIs

Peter Maydell committed 6 months ago

df055f4c39

target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config

Peter Maydell committed 6 months ago

7bec1d4428

hw/intc/arm_gicv5: Implement remaining set-config functions

Peter Maydell committed 6 months ago

f2ca526444

hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR

Peter Maydell committed 6 months ago

2ad2689070
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