hw/riscv/virt.c: fix 'iommu-map' FDT entry

Daniel Henrique Barboza committed 4 months ago

hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling

Jay Chang committed 4 months ago

hw/riscv: Don't insert DDT cache in Bare mode

Jay Chang committed 4 months ago

hw/riscv/numa.c: Supplement cpu topology arguments

Xuemei Liu committed 4 months ago

target/riscv: Reorder Smrnmi CPU fields above CPU reset line

Frank Chang committed 4 months ago

target/riscv: mask vxrm csrw write to the low 2 bits

Abhigyan Kumar committed 4 months ago

target/riscv: Improve alignment in riscv_cpu_dump_state

Anton Blanchard committed 4 months ago

target/riscv: Print privilege level and ELP in riscv_cpu_dump_state

Anton Blanchard committed 4 months ago

target/riscv: Add standard B extension implied rule

Frank Chang committed 4 months ago

target/riscv: Add the implied rule for G extension

Jim Shu committed 4 months ago

tests/functional: Add RISC-V endianness test

Djordje Todorovic committed 4 months ago

target/riscv: Expose and document the CPU 'big-endian' property

Djordje Todorovic committed 4 months ago

hw/riscv/boot: Honour data endianness

Djordje Todorovic committed 4 months ago

target/riscv: Add big-endian CPU configuration field and reset logic

Djordje Todorovic committed 4 months ago

hw/riscv/boot: Replace cpu_to_le32() -> const_le32()

Philippe Mathieu-Daudé committed 4 months ago

hw/riscv/boot: Rewrite setup_rom_reset_vec() using load/store API

Philippe Mathieu-Daudé committed 4 months ago

target/riscv: Fix page table walk endianness for big-endian harts

Djordje Todorovic committed 4 months ago

target/riscv: Remove target_ulong use in get_physical_address()

Philippe Mathieu-Daudé committed 4 months ago

target/riscv: De-indent some code in get_physical_address()

Philippe Mathieu-Daudé committed 4 months ago

target/riscv: Implement runtime data endianness via MSTATUS bits

Djordje Todorovic committed 4 months ago